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a/d flash mcu with eeprom HT66F0042/ht66f0082 revision: v1.30 date: de ? e ?? e ? 0 ?? ? 01 ? de ? e ?? e ? 0 ?? ? 01 ?
rev. 1.30 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 3 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tal ctts fats 6 cpu featu ? es .............................................................................................................................. ? pe ? iphe ? al featu ? es ...................................................................................................................... ? gene?al des??iption ............................................................................................. 7 sele?tion ta?le ..................................................................................................... 7 blo?k diag?a? ...................................................................................................... 8 pin assign?ent ........... ......................................................................................... 8 pin des??iption .......... ........................................................................................ 10 a?solute maxi?u? ratings .............................................................................. 1? d.c. cha?a?te?isti?s ........................................................................................... 17 a.c. cha?a?te?isti?s ........................................................................................... 19 adc ele?t?i?al cha?a?te?isti?s ... ..................................................................... ?0 lvr ele?t?i?al cha?a?te?isti?s .......................................................................... ?0 lcd ele?t?i?al cha?a?te?isti?s ......................................................................... ?1 powe? on reset ele?t?i?al cha?a?te?isti?s ...................................................... ?1 syste? a??hite?tu?e .......................................................................................... ?? clo ? king and pipelining .............................................................................................................. ?? p ? og ? a ? counte ? ........................................................................................................................ ? 3 sta ? k .......................................................................................................................................... ? 3 a ? ith ? eti ? and logi ? unit C alu ................................................................................................ ? 4 flash p?og?a? me?o?y ..................................................................................... ?? st ? u ? tu ? e ..................................................................................................................................... ?? spe ? ial ve ? to ? s .......................................................................................................................... ?? look-up ta ? le ............. ................................................................................................................ ?? ta ? le p ? og ? a ? exa ? ple ............................................................................................................. ?? in ci ?? uit p ? og ? a ?? ing .............................................................................................................. ? 7 on-chip de ? ug suppo ? t C ocds .............................................................................................. ? 8 ram data me?o?y ............................................................................................. ?9 st ? u ? tu ? e ..................................................................................................................................... ? 9 gene ? al pu ? pose data me ? o ? y ................................................................................................. ? 9 spe ? ial pu ? pose data me ? o ? y .................................................................................................. ? 9 spe?ial fun?tion registe? des??iption ............................................................ 3? indi ? e ? t add ? essing registe ? s C iar0 ? iar1 .............................................................................. 3 ? me ? o ? y pointe ? s C mp0 ? mp1 ................................................................................................... 3 ? bank pointe ? C bp ...................................................................................................................... 33 a ?? u ? ulato ? C acc .................................................................................................................... 33 p ? og ? a ? counte ? low registe ? C pcl ....................................................................................... 33 look-up ta ? le registe ? s C tblp ? tbhp ? tblh .......................................................................... 33 status registe ? C status ......................................................................................................... 34
rev. 1.30 ? de?e??e? 0?? ?01? rev. 1.30 3 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom eeprom data m 6 eeprom data me ? o ? y st ? u ? tu ? e ............................................................................................. 3 ? eeprom registe ? s ............ ....................................................................................................... 3 ? reading data f ? o ? the eeprom ............................................................................................. 38 w ? iting data to the eeprom ..................................................................................................... 38 w ? ite p ? ote ? tion .......................................................................................................................... 38 eeprom inte ?? upt ............. ........................................................................................................ 38 p ? og ? a ?? ing conside ? ations ............. ........................................................................................ 39 os?illato?s .......... ................................................................................................ 40 os ? illato ? ove ? view ............. ....................................................................................................... 40 system clock confgurations ..................................................................................................... 40 inte ? nal rc os ? illato ? C hirc ............. ....................................................................................... 41 inte ? nal 3 ? khz os ? illato ? C lirc ................................................................................................ 41 exte ? nal 3 ? .7 ? 8khz c ? ystal os ? illato ? C lxt ............. ................................................................ 41 supple ? enta ? y os ? illato ? ........................................................................................................... 43 ope?ating modes and syste? clo?ks ............................................................. 43 syste ? clo ? ks ........................................................................................................................... 43 syste ? ope ? ation modes ........................................................................................................... 44 cont ? ol registe ? ......................................................................................................................... 4 ? ope ? ating mode swit ? hing ........................................................................................................ 47 stand ? y cu ?? ent conside ? ations ................................................................................................ ?? wake-up ..................................................................................................................................... ?? wat?hdog ti?e? ........... ...................................................................................... ?3 wat ? hdog ti ? e ? clo ? k sou ?? e ................................................................................................... ? 3 wat ? hdog ti ? e ? cont ? ol registe ? ............. ................................................................................. ? 3 wat ? hdog ti ? e ? ope ? ation ........................................................................................................ ? 4 reset and initialisation ...................................................................................... ?? reset fun ? tions ............. ............................................................................................................ ?? reset initial conditions .............................................................................................................. ? 8 input/output po?ts ............................................................................................. ?? pull-high resisto ? s ..................................................................................................................... ?? po ? t a wake-up ............. ............................................................................................................. ? 3 i/o po ? t cont ? ol registe ? s .......................................................................................................... ? 3 pin-sha ? ed fun ? tions ............. .................................................................................................... ? 3 i/o po ? t sou ?? e cu ?? ent cont ? ol ................................................................................................. ? 9 i/o pin st ? u ? tu ? es ....................................................................................................................... 71 p ? og ? a ?? ing conside ? ations ............. ........................................................................................ 7 ?
rev. 1.30 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ti mls 2 int ? odu ? tion ................................................................................................................................ 7 ? tm ope ? ation ............. ................................................................................................................ 73 tm clo ? k sou ?? e ............. ........................................................................................................... 73 tm inte ?? upt ............. ................................................................................................................... 73 tm exte ? nal pins ........................................................................................................................ 73 tm input/output pin cont ? ol registe ? ........................................................................................ 74 p ? og ? a ?? ing conside ? ations ............. ........................................................................................ 74 co?pa?t type tm C ctm .................................................................................. 7? co ? pa ? t tm ope ? ation .............................................................................................................. 7 ? co ? pa ? t type tm registe ? des ?? iption ..................................................................................... 7 ? co ? pa ? t type tm ope ? ating modes ......................................................................................... 81 pe?iodi? type tm C ptm .................................................................................... 87 pe ? iodi ? tm ope ? ation ............. .................................................................................................. 87 pe ? iodi ? type tm registe ? des ?? iption ...................................................................................... 88 pe ? iodi ? type tm ope ? ating modes ........................................................................................... 9 ? analog to digital conve?te? .......... .................................................................. 101 a/d ove ? view ............. .............................................................................................................. 101 a/d conve ? te ? registe ? des ?? iption ......................................................................................... 10 ? a/d conve ? te ? data registe ? s C sadol ? sadoh ............. ...................................................... 10 ? a/d conve ? te ? cont ? ol registe ? s C sadc0 ? sadc1 ? sadc ? ............. ..................................... 10 ? a/d ope ? ation .......................................................................................................................... 10 ? su ?? a ? y of a/d conve ? sion steps ............. ............................................................................. 107 a/d t ? ansfe ? fun ? tion ............. ................................................................................................. 108 a/d p ? og ? a ?? ing exa ? ples .................................................................................................... 109 se?ial inte?fa?e module C sim ......................................................................... 111 spi inte ? fa ? e ............................................................................................................................ 111 i ? c inte ? fa ? e ............ ................................................................................................................. 117 uart inte?fa?e ................................................................................................ 1?7 uart exte ? nal pin inte ? fa ? e ............. ....................................................................................... 1 ? 8 uart data t ? ansfe ? s ? he ? e ................................................................................................... 1 ? 8 uart status and cont ? ol registe ? s ......................................................................................... 1 ? 8 baud rate gene ? ato ? ............................................................................................................... 134 uart setup and cont ? ol .......................................................................................................... 13 ? uart t ? ans ? itte ? ..................................................................................................................... 13 ? uart re ? eive ? ............. ........................................................................................................... 137 managing re ? eive ? e ?? o ? s ....................................................................................................... 139 uart module inte ?? upt st ? u ? tu ? e ............................................................................................. 140 uart powe ? down and wake-up ............................................................................................ 141 lcd scom fun?tion .......... .............................................................................. 14? lcd ope ? ation ............. ............................................................................................................ 14 ? lcd bias cu ?? ent cont ? ol ........................................................................................................ 14 ?
rev. 1.30 4 de?e??e? 0?? ?01? rev. 1.30 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tts 4 inte ?? upt registe ? s .................................................................................................................... 143 inte ?? upt ope ? ation ................................................................................................................... 1 ? 1 exte ? nal inte ?? upt ............. ......................................................................................................... 1 ?? multi-fun ? tion inte ?? upt ............................................................................................................. 1 ? 3 a/d conve ? te ? inte ?? upt ............................................................................................................ 1 ? 3 ti ? e base inte ?? upts ................................................................................................................ 1 ? 3 eeprom inte ?? upt ............. ...................................................................................................... 1 ? 4 tm inte ?? upts ............................................................................................................................ 1 ?? se ? ial inte ? fa ? e module inte ?? upt ............................................................................................. 1 ?? uart t ? ansfe ? inte ?? upt ........................................................................................................... 1 ?? inte ?? upt wake-up fun ? tion ...................................................................................................... 1 ?? p ? og ? a ?? ing conside ? ations ............. ...................................................................................... 1 ?? confguration options int ? odu ? tion .............................................................................................................................. 1 ? 8 inst ? u ? tion ti ? ing ..................................................................................................................... 1 ? 8 moving and t ? ansfe ?? ing data .................................................................................................. 1 ? 8 a ? ith ? eti ? ope ? ations ............................................................................................................... 1 ? 8 logi ? al and rotate ope ? ation .................................................................................................. 1 ? 9 b ? an ? hes and cont ? ol t ? ansfe ? ................................................................................................ 1 ? 9 bit ope ? ations .......................................................................................................................... 1 ? 9 ta ? le read ope ? ations ............................................................................................................ 1 ? 9 othe ? ope ? ations ............. ......................................................................................................... 1 ? 9 inst?u?tion set su??a?y .......... ...................................................................... 1?0 ta ? le conventions .................................................................................................................... 1 ? 0 instruction defnition ? 0-pin sop (300 ? il) outline di ? ensions ................................................................................ 17 ? ? 4-pin sop (300 ? il) outline di ? ensions ................................................................................ 173 ? 8-pin sop (300 ? il) outline di ? ensions ................................................................................ 174 ? 0-pin ssop (1 ? 0 ? il) outline di ? ensions .............................................................................. 17 ? ? 4-pin ssop (1 ? 0 ? il) outline di ? ensions .............................................................................. 17 ? ? 8-pin ssop (1 ? 0 ? il) outline di ? ensions .............................................................................. 177
rev. 1.30 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 7 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom fats cpu fats ? operatin g v oltage f sys = 8mhz: 2.2v~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 16mhz: 3.3v~5.5v ? up to 0.25s instruction cycle with 16mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? three oscillators internal rc C hirc internal 32khz rc C lirc external 32.768khz crystal C lxt ? fully intergrated internal 8/12/16mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 6-level subroutine nesting ? bit ma nipulation instruction ? flash program memory: 2k15/4k 16 ? ram data memory: 968/1288 ? true eeprom memory: 328/648 ? watchdog t imer function ? up to 26 bidirectional i/o lines ? software controlled 4-scom lines lcd driver with 1/2 bias ? two pin-shared external interrupts ? multiple t imer mo dules f or t ime m easure, c ompare m atch o utput, c apture i nput, pw m o utput, single pulse output functions ? dual t ime-base functions for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? serial interface module - spi or i 2 c ? full-duplex uni versal async hronous re ceiver a nd t ransmitter int erface C uar t ( ht66f0082 only) ? programmable i/o port source current for led driving applications ? low voltage reset function ? f lash program memory can be re-programmed up to 100,000 times ? f lash program memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years ? wide range of available package types
rev. 1.30 ? de?e??e? 0?? ?01? rev. 1.30 7 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom al dsiti these devices are flash memory type 8-bit high performance risc architecture microcontrollers. offering use rs t he c onvenience of fl ash me mory m ulti-programming fe atures, t hese de vices a lso include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of t rue eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter function. multiple and extremely flexible t imer mo dules p rovide t iming, p ulse g eneration, c apture i nput, c ompare m atch o utput, single pulse output and pwm generation functions. communication with the outside w orld is managed by including fully integrated spi and i 2 c interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal w atchdog t imer and low v oltage reset coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of internal and external, both low and high speed, oscillator functions are provided including fully integrated system oscillators which require no external components for their implementation. the ability to operate and switch dynamically between a range of operating modes using di fferent c lock sou rces gi ves use rs t he a bility t o op timise m icrocontroller op eration a nd minimise power consumption. the spi, i 2 c and uart interfaces of fer possibilities for data communication networks between microcontrollers, low-cos t data links betw een p cs and peripheral devices , portable and battery operated device communication, etc. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vices wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. most features are common to all devices, the main feature distinguishin g them are memory capacity , i/o count and package types. the following table summarises the main features of each device. ht ?? f004 ? ? k1 ? 9 ? 8 3 ? 8 ?? ? 1 ? - ? it8 ht ?? f008 ? 4k1 ? 1 ? 88 ? 48 ?? ? 1 ? - ? it8 pa?t no. ti?e? module ti?e base sim uart sta?k r-type lcd pa?kage ht ?? f004 ? 10- ? it ptm4 10- ? it ctm ? ? ? 4scom ? 0sop/ssop ? 4sop/ssop ht ?? f008 ? 10- ? it ptm4 10- ? it ctm ? ? ? 4scom ? 4sop/ssop ? 8sop/ssop
rev. 1.30 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 9 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom l diaa 8-?it risc mcu co?e i/o ti?e? modules flash p?og?a? me?o?y eeprom data me?o?y flash/eeprom p?og?a??ing ci??uit?y ram data me?o?y ti?e base wat?hdog ti?e? inte??upt cont?olle? reset ci??uit inte?nal rc os?illato?s lcd d?ive? sim (i ? c/spi) 1?-?it a/d conve?te? lxt os?illato? led d?ive? uart low voltage reset note: the uart function only exists in the ht66f0082. pc0/ptp1 pc1/ptck0/scom1 pc?/ctp0/res pa0/ptp0i_0/an?/icpda/ocdsda pa1/ptp0/an7 pa?/ctck0_0/i cpck/ocdsck pa3/ctp1/scom0 pb?/ptp?/scom? pb?/ptp3/scom3 avdd/vdd pb0/ptp1i/int0/an0/vref pb1/ptp3i_0/scs/an1/vrefo pb?/ptck3_0/int1/an? pa4/sdi/sda/an3 pa?/ptck?_0/sdo/an4 pa?/sck/scl/an? pb3/ctck1_0/xt1 pb4/ptck1_0/xt? pa7/ptp?i_0 avss/vss ?0 19 18 17 1? 1? 14 13 1? 11 1 ? 3 4 ? ? 7 8 9 10 ht??f004?/ht??v004? ?4 sop/ssop-a avss/vss pc0/ptp1 pc1/ptck0/scom1 pc?/ctp0/res pa0/ptp0i_0/an ?/icpda/ ocdsda pa1/ptp0/an7 pa?/ctck0_0/icpck/ocdsck pa3/ctp1/scom0 pb?/ptp?/scom? pb?/ptp3/scom3 avdd/vdd pb0/ptp1i/int0/an0/vref pb1/ptp3i_0/scs/an1/vrefo pb?/ptck3_0/int1/an? pa4/sdi/sda/an3 pa?/ptck?_0/sdo/an4 pa?/sck/scl/an? pa7/ptp?i_0 pb3/ctck1_0/xt1 pb4/ptck1_0/xt? pc3/ptp?i_1/scom? pc4/ctck1_1/scom3 pc?/ptck?_1 pc?/ptck3_1 ?4 ?3 ?? ?1 ?0 19 18 17 1? 1? 14 13 1 ? 3 4 ? ? 7 8 9 10 11 1?
rev. 1.30 8 de?e??e? 0?? ?01? rev. 1.30 9 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ht66f0082/ht660082 24 op/opa avss/vss pc0/ptp1 pc1/ptck0/scom1 pc?/ctp0/res pa0/ptp0i_0/an?/icpda/ocdsda pa1/ptp0/an7 pa?/ctck0_0/icpck/ocdsck pa3/ctp1/scom0 pb?/ptp?/scom? pb?/ptp3/scom3 avdd/vdd pb0/ptp1i/int0/an0/vref pb1/ptp3i_0/scs/an1/vrefo pb?/ptck3_0/int1/an? pa4/sdi/sda/an3 pa?/ptck?_0/sdo/an4 pa?/sck/scl/an? pa7/ptp?i_0 pb3/ctck1_0/xt1 pb4/ptck1_0/xt? pc3/ptp?i_1/scom? pc4/ctck1_1/scom3 pc?/ptck?_1/tx pc?/ptck3_1/rx ?4 ?3 ?? ?1 ?0 19 18 17 1? 1? 14 13 1 ? 3 4 ? ? 7 8 9 10 11 1? ht??f008?/ht??v008? ?8 sop/ssop-a avss/vss pc0/ptp1 pc1/ptck0/scom1 pc?/ctp0/res pa0/ptp0i_0/an ?/icpda/ ocdsda pa1/ptp0/an7 pa?/ctck0_0/icpck/ocdsck pa3/ctp1/scom0 pb?/ptp?/scom? avdd/vdd pb0/ptp1i/int0/an0/vref pb1/ptp3i_0/scs/an1/vrefo pb?/ptck3_0/int1/an? pa4/sdi/sda/an3 pa?/ptck?_0/sdo/an4 pa?/sck/scl/an? pa7/ptp?i_0 pb3/ctck1_0/xt1 pc3/ptp?i_1/scom? pc4/ctck1_1/scom3 pc?/ptck?_1/tx pc?/ptck3_1/rx pd0/ctck0_1/scom0 pd1/ptp0i_1/scom1 pd3/ptck1_1 pd?/ptp3i_1 pb?/ptp3/scom3 pb4/ptck1_0/xt? ?8 ?7 ?? ?? ?4 ?3 ?? ?1 ?0 19 18 17 1? 1? 1 ? 3 4 ? ? 7 8 9 10 11 1? 13 14 note: 1 . if t he p in-shared p in fu nctions h ave m ultiple o utputs si multaneously, t he d esired p in-shared fu nction is determined by the corresponding software control bits except the functions determined by the confguration options. 2. a vdd&vdd m eans t he vdd a nd a vdd a re t he do uble b onding. vss& avss m eans t he vss a nd avss are the double bonding. 3. the ocdsda and ocdsck pins are the ocds dedicated pins and only available for the ht66v0042 and ht66v0082 devices, which are the ocds ev chips for the HT66F0042 and ht66f0082 devices respectively.
rev. 1.30 10 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 11 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pi dsiti with the exceptio n of the power pins and some relevant transformer control pins, all pins on these devices c an be re ferenced by t heir port na me, e .g. p a0, p a1 e tc, whi ch re fer t o t he di gital i/ o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, t imer module pins etc. t he function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pa0/ptp0i_0/an ? / icpda/ocdsda pa0 pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ptp0i_0 pas0 ptm0c0 st ptm0 input an ? pas0 an a/d conve ? te ? input ? hannel ? icpda st cmos icp data line ocdsda st cmos on chip de ? ug syste ? data line (ocds ev only) pa1/ptp0/an7 pa1 pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ptp0 pas0 cmos ptm0 output an7 pas0 an a/d conve ? te ? input ? hannel 7 pa ? /ctck0_0/icpck/ ocdsck pa ? pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ctck0_0 ctm0c0 st ctm0 ? lo ? k input icpck st icp clo ? k line ocdsck st on chip de ? ug syste ? clo ? k line (ocds ev only) pa3/ctp1/scom0 pa3 pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ctp1 pas0 cmos ctm1output scom0 pas0 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pa4/sdi/sda/an3 pa4 pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up sdi pas1 simc0 st spi se ? ial data input sda pas1 simc0 st cmos i ? c data line an3 pas1 an a/d conve ? te ? input ? hannel 3 pa ? /ptck ? _0/sdo/ an4 pa ? pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ptck ? _0 pas1 ptm ? c0 ifs st ptm ? ? lo ? k input sdo pas1 cmos spi se ? ial data output an4 pas1 an a/d conve ? te ? input ? hannel 4
rev. 1.30 10 de?e??e? 0?? ?01? rev. 1.30 11 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pi a fti opt /t o/t dsiti pa ? /sck/scl/an ? pa ? pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up sck pas1 simc0 st cmos spi se ? ial ? lo ? k scl pas1 simc0 st cmos i ? c ? lo ? k line an ? pas1 an a/d conve ? te ? input ? hannel ? pa7/ptp ? i_0 pa7 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ptp ? i_0 ptm ? c0 ifs st ptm ? iutput pb0/ptp1i/int0/an0/ vref pb0 pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp1i pbs0 ptm1c0 st ptm1 iutput int0 pbs0 integ st exte ? nal inte ?? upt input an0 pbs0 an a/d conve ? te ? input ? hannel 0 vref pas0 an a/d conve ? te ? vref input pb1/ptp3i_0/scs/ an1/vrefo pb1 pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp3i_0 pbs0 ptm3c0 st ptm3 iutput scs pbs0 st cmos spi slave sele ? t pin an1 pbs0 an adc input ? hannel 1 vrefo pbs0 an a/d conve ? te ? ? efe ? en ? e voltage output pb ? /ptck3_0/int1/ an ? pb ? pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck3_0 pbs0 ptm3c0 ifs st ptm3 ? lo ? k input int1 pbs0 integ st exte ? nal inte ?? upt input an ? pbs0 an a/d conve ? te ? input ? hannel ? pb3/ctck1_0/xt1 pb3 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ctck1_0 ctm1c0 ifs st ctm1 ? lo ? k input xt1 co lxt lxt os ? illato ? pin pb4/ptck1_0/xt ? pb4 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck1_0 ptm1c0 st ptm1 ? lo ? k input xt ? co lxt lxt os ? illato ? pin pb ? /ptp3/scom3 pb ? pbpu pbs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp3 pbs1 cmos ptm3 output scom3 pbs1 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pb ? /ptp ? /scom ? pb ? pbpu pbs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp ? pbs1 cmos ptm ? output scom ? pbs1 an lcd d ? ive ? output fo ? lcd panel ? o ?? on
rev. 1.30 1 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 13 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pi a fti opt /t o/t dsiti pc0/ptp1 pc0 pcpu pcs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp1 pcs0 cmos ptm1 output pc1/ptck0/scom1 pc1 pcpu pcs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck0 pcs0 ptm0c0 st ptm0 ? lo ? k input scom1 pcs0 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pc ? /ctp0/ res pc ? pcpu pcs0 rstc st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ctp0 pcs0 rstc cmos ctm0 output res rstc st exte ? nal ? eset input pc3/ptp ? i_1/scom ? pc3 pcpu pcs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp ? i_1 pcs0 ptm ? c0 ifs st ptm ? input scom ? pcs0 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pc4/ctck1_1/ scom3 pc4 pcpu pcs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ctck1_1 pcs1 ctm1c0 ifs st ctm1 ? lo ? k input scom3 pcs1 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pc ? /ptck3_1 pc ? pcpu pcs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck3_1 pcs1 ptm3c0 ifs st ptm3 ? lo ? k input pc ? /ptck ? _1 pc ? pcpu pcs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck ? _1 pcs1 ptm ? c0 ifs st ptm ? ? lo ? k input avdd/ vdd vdd pwr digital positive powe ? supply avdd pwr analog positive powe ? supply avss/ vss vss pwr digital negative powe ? supply avss pwr analog negative powe ? supply note: i/t: input type o/t: output type op: optional by confguration option (co) or register option pwr: power st: schmitt t rigger input co: confguration option cmos: cmos output an: analog signal lxt: low frequency crystal oscillator as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins.
rev. 1.30 1? de?e??e? 0?? ?01? rev. 1.30 13 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ht66f0082 pi a fti opt /t o/t dsiti pa0/ptp0i_0/an ? / icpda/ocdsda pa0 pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ptp0i_0 pas0 ptm0c0 ifs st ptm0 input an ? pas0 an a/d conve ? te ? input ? hannel ? icpda st cmos icp data line ocdsda st cmos on chip de ? ug syste ? data line (ocds ev only) pa1/ptp0/an7 pa1 pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ptp0 pas0 cmos ptm0 output an7 pas0 an a/d conve ? te ? input ? hannel 7 pa ? /ctck0_0/icpck/ ocdsck pa ? pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ctck0_0 ctm0c0 ifs st ctm0 ? lo ? k input icpck st icp clo ? k line ocdsck st on chip de ? ug syste ? clo ? k line (ocds ev only) pa3/ctp1/scom0 pa3 pawu papu pas0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ctp1 pas0 cmos ctm1output scom0 pas0 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pa4/sdi/sda/an3 pa4 pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up sdi pas1 simc0 st spi se ? ial data input sda pas1 simc0 st cmos i ? c data line an3 pas1 an a/d conve ? te ? input ? hannel 3 pa ? /ptck ? _0/sdo/ an4 pa ? pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ptck ? _0 pas1 ptm ? c0 ifs st ptm ? ? lo ? k input sdo pas1 cmos spi se ? ial data output an4 pas1 an a/d conve ? te ? input ? hannel 4 pa ? /sck/scl/an ? pa ? pawu papu pas1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up sck pas1 simc0 st cmos spi se ? ial ? lo ? k scl pas1 simc0 st cmos i ? c ? lo ? k line an ? pas1 an a/d conve ? te ? input ? hannel ? pa7/ptp ? i_0 pa7 pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up ptp ? i_0 ptm ? c0 ifs st ptm ? iutput
rev. 1.30 14 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pi a fti opt /t o/t dsiti pb0/ptp1i/int0/an0/ vref pb0 pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp1i pbs0 ptm1c0 st ptm1 iutput int0 pbs0 integ st exte ? nal inte ?? upt input an0 pbs0 an a/d conve ? te ? input ? hannel 0 vref pas0 an a/d conve ? te ? vref input pb1/ptp3i_0/scs/ an1/vrefo pb1 pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp3i_0 pbs0 ptm3c0 ifs st ptm3 iutput scs pbs0 st cmos spi slave sele ? t pin an1 pbs0 an adc input ? hannel 1 vrefo pbs0 an a/d conve ? te ? ? efe ? en ? e voltage output pb ? /ptck3_0/int1/ an ? pb ? pbpu pbs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck3_0 pbs0 ptm3c0 ifs st ptm3 ? lo ? k input int1 pbs0 integ st exte ? nal inte ?? upt input an ? pbs0 an a/d conve ? te ? input ? hannel ? pb3/ctck1_0/xt1 pb3 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ctck1_0 ctm1c0 ifs st ctm1 ? lo ? k input xt1 co lxt lxt os ? illato ? pin pb4/ptck1_0/xt ? pb4 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck1_0 ptm1c0 ifs st ptm1 ? lo ? k input xt ? co lxt lxt os ? illato ? pin pb ? /ptp3/scom3 pb ? pbpu pbs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp3 pbs1 cmos ptm3 output scom3 pbs1 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pb ? /ptp ? /scom ? pb ? pbpu pbs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp ? pbs1 cmos ptm ? output scom ? pbs1 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pc0/ptp1 pc0 pcpu pcs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp1 pcs0 cmos ptm1 output pc1/ptck0/scom1 pc1 pcpu pcs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck0 pcs0 ptm0c0 st ptm0 ? lo ? k input scom1 pcs0 an lcd d ? ive ? output fo ? lcd panel ? o ?? on
rev. 1.30 14 de?e??e? 0?? ?01? rev. 1.30 1 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pi a fti opt /t o/t dsiti pc ? /ctp0/ res pc ? pcpu pcs0 rstc st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ctp0 pcs0 rstc cmos ctm0 output res rstc st exte ? nal ? eset input pc3/ptp ? i_1/scom ? pc3 pcpu pcs0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp ? i_1 pcs0 ptm ? c0 ifs st ptm ? input scom ? pcs0 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pc4/ctck1_1/ scom3 pc4 pcpu pcs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ctck1_1 pcs1 ctm1c0 ifs st ctm1 ? lo ? k input scom3 pcs1 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pc ? /ptck3_1/rx pc ? pcpu pcs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck3_1 pcs1 ptm3c0 ifs st ptm3 ? lo ? k input rx pcs1 st uart ? e ? eive ? pin (only fo ? ht ?? f008 ? ) pc ? /ptck ? _1/tx pc ? pcpu pcs1 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck ? _1 pcs1 ptm ? c0 ifs st ptm ? ? lo ? k input tx pcs1 cmos uart t ? ans ? itte ? pin (only fo ? ht ?? f008 ? ) pd0/ctck0_1/ scom0 pd0 pdpu pds0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ctck0_1 pds0 ctm0c0 ifs st ctm0 ? lo ? k input scom0 pds0 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pd1/ptp0i_1/scom1 pd1 pdpu pds0 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp0i_1 pds0 ptm0c0 ifs st ptm0 input scom1 pds0 an lcd d ? ive ? output fo ? lcd panel ? o ?? on pd ? /ptp3i_1 pd ? pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptp3i_1 ptm3c0 ifs st ptm3 input pd3/ptck1_1 pc3 pcpu rstc st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up ptck1_1 ptm1c0 ifs st ptm1 ? lo ? k input
rev. 1.30 1 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 17 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pi a fti opt /t o/t dsiti avdd/ vdd vdd pwr digital positive powe ? supply avdd pwr analog positive powe ? supply avss/ vss vss pwr digital negative powe ? supply avss pwr analog negative powe ? supply note: i/t: input type o/t: output type op: optional by confguration option(co) or register option pwr: power st: schmitt t rigger input co: confguration option cmos: cmos output an: analog signal lxt: low frequency crystal oscillator as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. supply v oltage .............. ...................................................................................... v ss -0.3v to v ss +6.0v input v oltage .............. ........................................................................................ v ss -0.3v to v dd +0.3v storage t emperature ............... ...................................................................................... -50c to 125c operating t emperature .............. ...................................................................................... -40c to 85c i ol t otal .............. ................................................................................................... ....................... 80ma i oh t otal .............. ......................................................................................................................... -80ma total power dissipation .............. .............................................................................................. 500mw note: thes e are s tress ratings only . s tresses exceeding the range s pecified under a bsolute maximum ratings may cause substantial damage to the devices. functional operation of these devices at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability.
rev. 1.30 1? de?e??e? 0?? ?01? rev. 1.30 17 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom dc chaatistis ta = ?? c sy??ol pa?a?ete? test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage (hirc) f sys =f hirc =8mhz ? . ? ? . ? v f sys =f hirc =1 ? mhz ? .7 ? . ? v f sys =f hirc =1 ? mhz 3.3 ? . ? v ope ? ating voltage (lxt) f sys =f lxt =3 ? 7 ? 8hz ? . ? ? . ? v ope ? ating voltage (lirc) f sys =f lirc =3 ? khz ? . ? ? . ? v i dd ope ? ating cu ?? ent (hirc) 3v no load ? f sys =f hirc =8mhz ? adc off ? wdt ena ? le ? lvr ena ? le 1.0 ? .0 ? a ? v ? . ? 4.0 ? a 3v no load ? f sys =f hirc =1 ? mhz ? adc off ? wdt ena ? le ? lvr ena ? le 1. ? ? . ? ? a ? v 3. ? ? . ? ? a ? v no load ? f sys =f hirc =1 ? mhz ? adc off ? wdt ena ? le ? lvr ena ? le 4. ? 7.0 ? a ope ? ating cu ?? ent (lxt) 3v no load ? f sys =f lxt =3 ? 7 ? 8hz ? adc off ? wdt ena ? le ? lvr ena ? le ? lxtlp=0 ? 0 40 a ? v 40 80 a 3v no load ? f sys =f lxt =3 ? 7 ? 8hz ? adc off ? wdt ena ? le ? lvr ena ? le ? lxtlp=1 1 ? 30 a ? v 30 ? 0 a ope ? ating cu ?? ent (lirc) 3v no load ? f sys =f licrc =3 ? khz ? adc off ? wdt ena ? le ? lvr ena ? le 1 ? 30 a ? v 30 ? 0 a ope ? ating cu ?? ent ? no ?? al mode ? f h =1 ? mhz (hirc) ? v no load ? f sys =f h / ?? adc off ? wdt ena ? le ? lvr ena ? le 3.0 4.0 ? a ? v no load ? f sys =f h / ? 4 ? adc off ? wdt ena ? le ? lvr ena ? le 1. ? ? . ? ? a ope ? ating cu ?? ent ? no ?? al mode ? f h =1 ? mhz (hirc) 3v no load ? f sys =f h / ?? adc off ? wdt ena ? le ? lvr ena ? le 1. ? ? . ? ? a ? v ? . ? 3.0 ? a 3v no load ? f sys =f h / ? 4 ? adc off ? wdt ena ? le ? lvr ena ? le 0.7 1. ? ? a ? v 1. ? 1. ? ? a ope ? ating cu ?? ent ? no ?? al mode ? f h =8mhz (hirc) 3v no load ? f sys =f h / ?? adc off ? wdt ena ? le ? lvr ena ? le 1.0 1. ? ? a ? v 1. ? ? .0 ? a 3v no load ? f sys =f h / ? 4 ? adc off ? wdt ena ? le ? lvr ena ? le 0. ? 0.8 ? a ? v 0.8 1.1 ? a
rev. 1.30 18 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 19 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom l paat tst citis mi t ma uit dd citis i stb sleep0 mode stand ? y cu ?? ent (lirc and lxt off) 3v no load ? all pe ? iphe ? als off ? wdt off 0. ? 0.8 a ? v 0. ? 1.0 a sleep1 mode stand ? y cu ?? ent (lirc on) 3v no load ? adc off ? wdt ena ? le ? lvr disa ? le 1.3 3.0 a ? v ? .0 10 a sleep1 mode stand ? y cu ?? ent (lxt on) 3v no load ? adc off ? wdt ena ? le ? lvr disa ? le ? lxtlp=0 ? .0 4.0 a ? v 4.0 ? .0 a 3v no load ? adc off ? wdt ena ? le ? lvr disa ? le ? lxtlp=1 1. ? 3.0 a ? v 3.0 ? .0 a idle0 mode stand ? y cu ?? ent (lirc on) 3v no load ? adc off ? wdt ena ? le ? lvr disa ? le 1.3 3.0 a ? v ? .0 10 a idle0 mode stand ? y cu ?? ent (lxt on) 3v no load ? adc off ? wdt ena ? le ? lvr disa ? le ? lxtlp=0 ? .0 4.0 a ? v 4.0 ? .0 a 3v no load ? adc off ? wdt ena ? le ? lvr disa ? le ? lxtlp=1 1. ? 3.0 a ? v 3.0 ? .0 a idle1 mode stand ? y cu ?? ent (hirc on) 3v no load ? adc off ? wdt ena ? le ? f sys =f hirc =8mhz on 0.8 1. ? ? a ? v 1.0 ? .0 ? a 3v no load ? adc off ? wdt ena ? le ? f sys =f hirc =1 ? mhz on 1. ? ? .4 ? a ? v 1. ? 3.0 ? a ? v no load ? adc off ? wdt ena ? le ? f sys =f hirc =1 ? mhz on ? .0 4.0 ? a v il input low voltage fo ? i/o po ? ts o ? input pins ex ? ept res pin ? v 0 1. ? v 0 0. ? v dd v input low voltage fo ? res pin 0 0.4v dd v v ih input high voltage fo ? i/o po ? ts o ? input pins ex ? ept res pin ? v 3. ? ? .0 v 0.8v dd v dd v input high voltage fo ? res pin 0.9v dd v dd v i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd 18 3 ? ? a ? v v ol =0.1v dd 40 80 ? a i oh i/o po ? t ? sou ?? e cu ?? ent 3v v oh =0.9v dd ? pxps=00 -1.0 - ? .0 ? a ? v v oh =0.9v dd ? pxps=00 - ? .0 -4.0 ? a 3v v oh =0.9v dd ? pxps=01 -1.7 ? -3. ? ? a ? v v oh =0.9v dd ? pxps=01 -3. ? -7.0 ? a 3v v oh =0.9v dd ? pxps=10 - ? . ? - ? .0 ? a ? v v oh =0.9v dd ? pxps=10 - ? .0 -10 ? a 3v v oh =0.9v dd ? pxps=11 - ? . ? -11 ? a ? v v oh =0.9v dd ? pxps=11 -11 - ?? ? a r ph pull-high resistan ? e fo ? i/o po ? ts 3v ? 0 ? 0 100 k ? v 10 30 ? 0 k i ocds ope ? ating cu ?? ent ? no ?? al mode ? f sys =f h (hirc) (fo ? ocds ev testing ? conne ? t to an e-link) 3v no load ? f h =8mhz ? adc off ? wdt ena ? le 1.4 ? .0 ? a
rev. 1.30 18 de?e??e? 0?? ?01? rev. 1.30 19 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ac chaatistis ta= ?? c sy??ol pa?a?ete? test conditions min. typ. max. unit v dd condition f sys syste ? clo ? k (hirc) ? . ? v~ ? . ? v f sys =f hirc =8mhz 8 mhz ? .7v~ ? . ? v f sys =f hirc =1 ? mhz 1 ? mhz 3.3v~ ? . ? v f sys =f hirc =1 ? mhz 1 ? mhz syste ? clo ? k (lxt) ? . ? v~ ? . ? v f sys =f lxt =3 ? 7 ? 8hz 3 ? 7 ? 8 hz syste ? clo ? k (lirc) ? . ? v~ ? . ? v f sys =f lirc =3 ? khz 3 ? khz f hirc high speed inte ? nal rc os ? illato ? (hirc t ? i ? @ v dd =3v/ ? v ? ta= ?? c) ? . ? v~ ? . ? v ta= -40c to 8 ? c -3% 8 +3% mhz ? .7v~ ? . ? v -3% 1 ? +3% mhz 3.3v~ ? . ? v -3% 1 ? +3% mhz f lirc syste ? clo ? k ( 3 ? khz rc os ? illato ? ) ? . ? v~ ? . ? v ta= -40c to 8 ? c 8 3 ? ? 0 khz f lxt syste ? clo ? k (3 ? 7 ? 8hz c ? ystal os ? illato ? ) ? . ? v~ ? . ? v ta= ?? c 3 ? 7 ? 8 hz t tck xtckn ? ptpni input pulse width 0.3 s t res exte ? nal reset low pulse width 10 s t int inte ?? upt pulse width 0.3 s t eerd eeprom read ti ? e ? 4 t sys t eewr eeprom w ? ite ti ? e ? ? . ? ? s t sst syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt ? f sys off at halt state ? reset pin reset) f sys =lxt 10 ? 4 t sys f sys =hirc 1 ? f sys =lirc ? syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt ? f sys on at halt state) ? t sys t rstd syste ? reset delay ti ? e (powe ? on reset ? lvr reset ? wdt s/w reset (wdtc) ? . ?? ? 0 1 ?? ? s syste ? reset delay ti ? e (res pin reset ? wdt no ?? al reset) ? .08 1 ? .7 47.9 ? s f i ? c i ? c standa ? d mode (100khz) f sys f ? equen ? y no ? lo ? k de ? oun ? e ? mhz ? syste ? ? lo ? k de ? oun ? e 4 mhz 4 syste ? ? lo ? k de ? oun ? e 8 mhz i ? c fast mode (400khz) f sys f ? equen ? y no ? lo ? k de ? oun ? e ? mhz ? syste ? ? lo ? k de ? oun ? e 10 mhz 4 syste ? ? lo ? k de ? oun ? e ? 0 mhz 1rwh w sys i sys pdd dffudf i udo foodu iutf d fso fdsdfu o ff d d ofd d fo yf d so
rev. 1.30 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?1 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom adc eltial chaatistis ta= ?? c sy??ol pa?a?ete? test conditions min. typ. max. unit v dd conditions av dd a/d conve ? te ? ope ? ating voltage ? .7 ? . ? v v adi a/d conve ? te ? input voltage 0 av dd /v ref v v ref a/d conve ? te ? refe ? en ? e voltage 3v ? av dd v ? v dnl diffe ? ential non-linea ? ity ? .7v v ref =av dd =v dd t adck =0.5s -3 +3 lsb 3v ? v inl integ ? al non-linea ? ity ? .7v v ref =av dd =v dd t adck =0.5s -4 +4 lsb 3v ? v i adc additional powe ? consu ? ption if a/d conve ? te ? is used 3v no load (t adck =0.5s ) 1.0 ? .0 ? a ? v no load (t adck =0.5s ) 1. ? 3.0 ? a t adck a/d conve ? te ? clo ? k pe ? iod ? .7v~ ? . ? v 0. ? 10 s t adc a/d conve ? sion ti ? e (in ? lude sa ? ple and hold ti ? e) ? .7~ ? . ? v 1 ? - ? it adc 1 ? ? 0 t adck t ads a/d conve ? te ? sa ? pling ti ? e ? .7v~ ? . ? v 4 t adck t on ? st a/d conve ? te ? on-to-sta ? t ti ? e ? .7v~ ? . ? v 4 s v dd ope ? ating voltage 1.9 ? . ? v v lvr low voltage reset voltage lvr ena ? le ? ? .1v option - ? % ? .1 + ? % v bufo refe ? en ? e output with buffe ? t j = + ?? c@3.1 ? v - ? % 1.04 + ? % v t lvr low voltage width to reset 1 ? 0 3 ? 0 ? 40 s
rev. 1.30 ?0 de?e??e? 0?? ?01? rev. 1.30 ? 1 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom cd eltial chaatistis l paat tst citis mi t ma uit dd citis i bias v dd / ? bias cu ?? ent fo ? lcd ? v isel[1:0]=00 17. ? ?? .0 3 ? . ? a isel[1:0]=01 3 ? ? 0 ?? a isel[1:0]=10 70 100 130 a isel[1:0]=11 140 ? 00 ?? 0 a v scom v dd / ? voltage fo ? lcd com po ? t ? . ? v~ ? . ? v no load 0.47 ? 0. ? 00 0. ??? v dd powe? on reset ele?t?i?al cha?a?te?isti?s ta= ?? c sy??ol pa?a?ete? test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to ensu ? e powe ? -on reset 100 ? v rr por v dd rising rate to ensu ? e powe ? -on reset 0.03 ? v/ ? s t por mini ? u ? ti ? e fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ? s v dd t por rr por v por ti?e
rev. 1.30 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?3 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom st ahitt a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the device takes advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal regis ters are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility . this makes these devices suitable for low-cost, high-volume production for controller applications the main system clock, derived from either a hirc, lxt or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. fet?h inst. (pc) (syste? clo?k) f sys phase clo?k t1 phase clo?k t? phase clo?k t3 phase clo?k t4 p?og?a? counte? pc pc+1 pc+? pipelining exe?ute inst. (pc-1) fet?h inst. (pc+1) exe?ute inst. (pc) fet?h inst. (pc+?) exe?ute inst. (pc+1) syste? clo?k and pipelining for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications.
rev. 1.30 ?? de?e??e? 0?? ?01? rev. 1.30 ? 3 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom fet?h inst. 1 1 mov a?[1?h] ? call delay 3 cpl [1?h] 4 : ? : ? delay: nop exe?ute inst. 1 fet?h inst. ? exe?ute inst. ? fet?h inst. 3 flush pipeline fet?h inst. ? exe?ute inst. ? fet?h inst. 7 inst?u?tion fet?hing p?og?a? counte? during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. ht ?? f004 ? pc10~pc8 pcl7~pcl0 ht ?? f008 ? pc11~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jum ps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced . this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost.
rev. 1.30 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom
device stack levels ht ?? f004 ? ? ht ?? f008 ? a?ith?eti? and logi? unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement: inca, inc, deca, dec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.30 ?4 de?e??e? 0?? ?01? rev. 1.30 ?? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom flash pa m the program memory is the location where the user code or program is stored. for these devices the program memory are flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, these flash devices of fer users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. the program memory has a capaci ty of 2k15 or 4k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. t able data, which c an b e se tup i n a ny l ocation wi thin t he pro gram me mory, i s a ddressed b y a se parate t able pointer register. ht ?? f004 ? ? k1 ? ? its ht ?? f008 ? 4k1 ? ? its 0000h reset inte??upt ve?to? 0004h 00?8h 7ffh 1? ?its reset inte??upt ve?to? 1? ?its ht??f004? ht??f008? 00?ch fffh p?og?a? me?o?y st?u?tu?e spe?ial ve?to?s within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by these devices reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.
rev. 1.30 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?7 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tal any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer registers, tbhp and tblp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd [m] or t abrdl [m] instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is f00h which refers to the start address of the last page within the 4k words program memory of the ht66f0082 device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address f06h or 6 loca tions after the start of the last page. note that the value for the table pointer is referenced to the frst address of the specifed page that tbhp points to if the t abrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.30 ?? de?e??e? 0?? ?01? rev. 1.30 ? 7 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tal ra pa eal tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : mov a, 06h ; initialise low table pointer - note that this address is referenced mov tblp, a ; to the last page or the page that tbhp pointed mov a, 0fh ; initialise high table pointer mov tbhp, a : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 0f06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 0f05h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : org 0f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : n circuit rogramming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. icpda pa0 p ? og ? a ?? ing se ? ial data icpck pa ? p ? og ? a ?? ing se ? ial clo ? k vdd vdd powe ? supply vss vss g ? ound the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo additional lines are required for the power supply and ground. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature.
rev. 1.30 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?9 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom
note: * may be resistor or capacito r. the resistance of * must be great er than 1k or the capacitance of * must be less than 1nf. there are two ev mcu devices, ht66v0042 and ht66v0082, which are used to emulate the HT66F0042 and ht66f0082 mcus. these ev devices also provide an on-chip debug function to de bug t he de vice duri ng t he de velopment proc ess. t he e v mcus a nd t he a ctual mcu de vices are almost functionally compatible except for the on-chip debug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/ output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, ot her func tions whi ch a re sha red wi th t he ocdsda a nd ocdsck pi ns i n t he a ctual mcu device will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for a more detailed ocds description, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. ocdsda ocdsda on- ? hip de ? ug suppo ? t data/add ? ess input/output ocdsck ocdsck on- ? hip de ? ug suppo ? t clo ? k input vdd vdd powe ? supply gnd vss g ? ound
rev. 1.30 ?8 de?e??e? 0?? ?01? rev. 1.30 ? 9 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ram data m the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. ht ?? f004 ? 9 ? 8 80h~dfh 40h eec ? egiste ? only ht ?? f008 ? 1 ? 88 80h~ffh 40h eec ? egiste ? only data me?o?y st?u?tu?e gene?al pu?pose data me?o?y there are 96 or 128 bytes of general purpose data memory which are located in bank 0. all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later . it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value 00h.
rev. 1.30 30 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 31 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 00h iar 0 01h mp 0 0?h iar 1 03h mp 1 04h 0?h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh pb 0 ch pc 0 dh ptm 1 rph 0 eh pcc 0 fh ctm 1 dh 10h ptm 0 rph 11h 1?h 19h mfi 0 18h intc ? 1 bh 1 ah 1 dh 1 ch 1 fh mfi 1 mfi ? 1 eh smod 13h 14h ptm 1 dl 1?h ptm 1 dh 1?h 17h ptm 1 al bank 0~1 pcpu pbpu unused pac papu pawu wdtc tbc scomc sadol sadoh sadc 1 sadc ? rstc pas 1 pbs 0 pbs 1 ptm 0c1 ptm 0 dl ptm 0 rpl ?0h ?1h ??h ?9h ?8h ? bh ? ah ? dh ? ch ? fh ? eh ?3h ?4h ??h ??h ?7h 30h 31h 3?h 39h 38h 3 bh 3 ah 3 dh 3 ch 3 fh 3 eh 33h 34h 3?h 3?h 37h 40h eec 41h eea 4?h eed 43h 47h ptm 3c0 48h ptm ?c1 49h ptm 3c1 4 ah ptm 3 dl 4 bh ptm 3 dh 4 ch ptm 3 al 4 dh ptm ? rpl 4 eh 4 fh ?0h ?1h ??h ?8h ?3h ?4h ??h ??h ?7h bank 0 bank 1 unused ptm ?c0 ptm ? dl ptm ? dh ptm ? al ptm ? ah ptm 3 ah ?0h ?1h bp integ intc 0 intc 1 pa smod 1 sadc 0 pas 0 unused ptm 0 dh ptm 1c0 ptm 1 ah ptm 1 rpl pbc 44h 4?h 4?h ?9h ? ah ? bh ? ch ? dh ? eh ? fh ctm 0c0 ctm 0c1 ctm 0 ah ctm 1c0 ctm 1c1 ??h ?3h ?4h ??h ??h ?7h ?8h ?9h ctm 1 dl ctm 1 al ctm 1 ah simc 0 ? ah ? bh ? dh ? ch ? eh simc 1 simc ?/ sima simd simtoc 7 fh : unused ? ?ead as 00h pcs 0 pcs 1 ifs ptm 0c0 ptm 0 al sledc 0 sledc 1 ptm 3 rpl ptm 3 rph ctm 0 dl ctm 0 dh ctm 0 al unused unused unused unused ptm 1c1 unused unused ptm ? rph unused unused ptm 0 ah unused spe?ial pu?pose data me?o?y st?u?tu?e C ht??f004?
rev. 1.30 30 de?e??e? 0?? ?01? rev. 1.30 31 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 00h iar 0 01h mp 0 0?h iar 1 03h mp 1 04h 0?h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh pb 0 ch pc 0 dh ptm 1 rph 0 eh pcc 0 fh ctm 1 dh 10h ptm 0 rph 11h 1?h 19h mfi 0 18h intc ? 1 bh 1 ah 1 dh 1 ch 1 fh mfi 1 mfi ? 1 eh smod 13h 14h ptm 1 dl 1?h ptm 1 dh 1?h 17h ptm 1 al bank 0~1 pcpu pbpu unused pac papu pawu wdtc tbc scomc sadol sadoh sadc 1 sadc ? rstc pas 1 pbs 0 pbs 1 ptm 0c1 ptm 0 dl ptm 0 rpl ?0h ?1h ??h ?9h ?8h ? bh ? ah ? dh ? ch ? fh ? eh ?3h ?4h ??h ??h ?7h 30h 31h 3?h 39h 38h 3 bh 3 ah 3 dh 3 ch 3 fh 3 eh 33h 34h 3?h 3?h 37h 40h eec 41h eea 4?h eed 43h 47h ptm 3c0 48h ptm ?c1 49h ptm 3c1 4 ah ptm 3 dl 4 bh ptm 3 dh 4 ch ptm 3 al 4 dh ptm ? rpl 4 eh 4 fh ?0h ?1h ??h ?8h ?3h ?4h ??h ??h ?7h bank 0 bank 1 unused ptm ?c0 ptm ? dl ptm ? dh ptm ? al ptm ? ah ptm 3 ah ?0h ?1h bp integ intc 0 intc 1 pa smod 1 sadc 0 pas 0 unused ptm 0 dh ptm 1c0 ptm 1 ah ptm 1 rpl pbc 44h 4?h 4?h ?9h ? ah ? bh ? ch ? dh ? eh ? fh ctm 0c0 ctm 0c1 ctm 0 ah ctm 1c0 ctm 1c1 ??h ?3h ?4h ??h ??h ?7h ?8h ?9h ctm 1 dl ctm 1 al ctm 1 ah simc 0 ? ah ? bh ? dh ? ch ? eh simc 1 simc ?/ sima simd simtoc 7 fh : unused ? ?ead as 00h pcs 0 pcs 1 ifs ptm 0c0 ptm 0 al ptm 0 ah sledc 0 sledc 1 ptm 3 rpl ptm 3 rph ctm 0 dl ctm 0 dh ctm 0 al unused unused unused unused unused ptm 1c1 unused unused unused pd pdc pdpu pds 0 usr ? fh 70h 71h 7?h 73h ucr 1 ucr ? txr _ rxr brg 74h 7?h 7?h 77h unused ptm ? rph spe?ial pu?pose data me?o?y st?u?tu?e C ht??f008?
rev. 1.30 3 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 33 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ial fti rist dsiti most of the special function register details will be described in the relevant functional sections, however several registers require a separate description in this section. the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org00h start: m ov a,04h ; setup size of block m ov block,a mov a ,offset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0,a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.30 3? de?e??e? 0?? ?01? rev. 1.30 33 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom a pit p for this series of devices, the data memory is divided into two banks, bank0 and bank1. selecting the required data memory area is achieved using the bank pointer . bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addressi ng the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from bank1 must be implemented using indirect addressing. na ? e dmbp0 r/w r/w por 0 bit 7 ~ 1 unimplemented, read as 0 bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. these three special function registers are used to control operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.30 34 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 3? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tats rist tatu this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also af fected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power -up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cle ared by a system power -up or executing the clr wdt or hal t instruction. to is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.30 34 de?e??e? 0?? ?01? rev. 1.30 3 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tatu rist it 6 4 2 0 na ? e to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 "" unknown bit 7~6 unimplemented, read as 0 bit 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.30 3 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 37 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom eeprom data m these d evices c ontain a n a rea o f i nternal e eprom da ta me mory. e eprom, wh ich st ands f or electrically erasable programmable read only memory , is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. by incorporating this kind of d ata m emory, a wh ole n ew h ost o f a pplication p ossibilities a re m ade a vailable t o t he d esigner. the a vailability o f e eprom st orage a llows i nformation su ch a s p roduct i dentifcation n umbers, calibration values , s pecifc us er data, s ystem s etup data or other product information to be s tored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. the eeprom data memory capac ity is 328 bits or 648 bits for this series of devices. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using one address register and one data register in bank 0 and a single control register in bank 1. ht ?? f004 ? 3 ? 8 ? its ht ?? f008 ? ? 48 ? its eeprom registe?s three registers control the overall operation of the internal eeprom data memory . these are the address registers, eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special functi on regist er. the eec register however , be ing located in bank1, cannot be di rectly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eea C ht ?? f004 ? d4 d3 d ? d1 d0 eea C ht ?? f008 ? d ? d4 d3 d ? d1 d0 eed d7 d ? d ? d4 d3 d ? d1 d0 eec wren wr rden rd eeprom cont?ol registe?s list eea registe? C ht??f004? bit 7 ? ? 4 3 ? 1 0 na ? e d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~ 5 unimplemented, read as 0 bit 4 ~ 0 data eeprom address data eeprom address bit 4 ~ bit 0
rev. 1.30 3? de?e??e? 0?? ?01? rev. 1.30 37 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom eea rist ht66f0082 it 6 4 2 0 na ? e d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as 0 bit 5 ~ 0 data eeprom address data eeprom address bit 5 ~ bit 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 data eeprom data data eeprom data bit 7 ~ bit 0 na ? e wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as 0 bit 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set hi gh by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.30 38 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 39 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom rai data th eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. to write data to the eeprom, the eeprom address of the data to be written must frst be placed in t he ee a regist er and t he dat a pla ced in t he ee d regist er. then t he writ e enabl e bit , wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the e ec r egister m ust be i mmediately se t hi gh t o i nitiate a wri te c ycle. t hese t wo i nstructions must be executed consecutively . the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. protection against inadvertent w rite operation is provided in several ways . after the devices are powered-on the w rite enable bit in the control register will be cleared preventing any write operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register . when an eeprom write cycle ends, the def request fag will be set. if the global, eeprom interrupt are enabled and the stack is not full, a subroutine call to the eeprom interrupt vector , will take place. when the eeprom interrupt is serviced, the eeprom interrupt fag def will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.30 38 de?e??e? 0?? ?01? rev. 1.30 39 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pai csiatis care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank1where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycl e starts. note that the devices should not enter the id le or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, 0 40h ; s etup m emory p ointer m p1 mov mp1, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; s etup b ank p ointer mov bp, a set iar1.1 ; s et r den b it, e nable r ead o perations set iar1.0 ; s tart r ead c ycle - s et r d b it back: sz iar1.0 ; c heck f or r ead c ycle e nd jmp back clr iar1 ; d isable e eprom w rite clr bp mov a, ee d ; m ove re ad d ata t o re gister mov read_data, a mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, e eprom_data ; u ser d efned da ta mov eed, a mov a, 0 40h ; s etup m emory p ointer m p1 mov mp1, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; s etup b ank p ointer mov bp, a clr emi set iar1.3 ; s et w ren b it, e nable w rite o perations set iar1.2 ; s tart w rite c ycle - s et w r b itC e xecuted i mmediately ; a fter s et w ren b it set emi back: sz iar1.2 ; c heck f or w rite c ycle e nd jmp back clr iar1 ; d isable e eprom w rite clr bp
rev. 1.30 40 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 41 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom osillats various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and control registers. the devices include two internal oscillators and an external oscillator. in addition to being the source of the main system clock the oscillators also provide clock sources for the w atchdog t imer, t ime bases and tms. external oscillator requiring some external components as well as fully integrated internal oscillators requiring no exte rnal components, are provided to form a wide range of both fast and slow system oscillators. the low speed oscillators are selected through the confguration option. the h igher f requency o scillators p rovide h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capabilit y of dynamically switching between fast and slow system clock, the devices have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. inte ? nal high speed rc hirc 8/1 ? /1 ? mhz inte ? nal low speed rc lirc 3 ? khz exte ? nal low speed c ? ystal lxt 3 ? .7 ? 8khz xt1/xt ? os?illato? types system clock confgurations there are three methods of generating the system clock, a high speed oscillator and two low speed oscillators. the high speed oscillato r is the internal 8mhz, 12mhz, 16mhz rc oscillator . the two low speed oscillators are the internal 32khz oscillator , lirc, and the external 32.768khz crystal oscillator, lxt . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. the a ctual so urce c lock u sed f or t he l ow sp eed o scillator i s c hosen v ia c onfguration o ption. t he frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register . note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator.
rev. 1.30 40 de?e??e? 0?? ?01? rev. 1.30 41 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom hirc p?es?ale? f h lirc low speed os?illato?s f h /? f h /1? f h /?4 f h /8 f h /4 f h /3? hlclk cks?~cks0 ?its f sys f l high speed os?illato? lxt configu?ation option system oscillator confgurations the internal high speed rc oscillator , hirc, is a fully integrated system oscillator requiring no external c omponents. t he osc illator c an be se lected t o be e ither 8mhz , 12mhz or 16mhz vi a the c onfguration o ption. de vice t rimming d uring t he m anufacturing p rocess a nd t he i nclusion o f internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. the internal 32khz system oscillat or is one of the low frequency oscillators. it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is s elected via configuration option. the 32.768kh z crystal o scillator also includes an internal resistor and capacitor , which is also selected via confguration option. selecting this option may eliminate the need for external components c1, c2 and r p . in this case it is only required to connect a 32.768khz crystal to pins xt1 and xt2. when the configuration selects the external resistor and capacitor , after a 32.768khz crystal is connected between pins xt1 and xt2, the external resistor and capacitor components may be necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to dif ferent crystal manufacturing tolerances. during power -up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microco ntroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. t o do this, another clock, independent of the system clock, must be provided.
rev. 1.30 4 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 43 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specifcation. the external parallel feedback resistor , rp, is required. note that the wire connected between the 32.768khz crystal and the xt1/xt2 pins should be kept as short as possible to minimize the stray noise interface. the confguration option determines if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins or other pin-shared functions. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins or other pin-shared functions. ? if t he l xt osc illator i s use d for any c lock sourc e, a 32.768khz c rystal shoul d be c onnected t o the xt1/xt2 pins. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible. r p 3?.7?8khz c1 c? r p1 c3 c4 xt1 xt? to inte?nal ci??uits inte?nal rc note: 1. when the lxt confguration option selects the external resistor and capacitor , then the r , c1 and c2 components are required. 2. when the lxt confguration option selects the integrated resistor and capacitor , it is only necessary to connect the 32.768khz crystal between pins xt1 and xt2 3. although not shown , pins have a parasitic capacitance of around 7pf. external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 3 ? .7 ? 8khz 8pf 10pf note: 1. c1 and c ? values a ? e fo ? guidan ? e only. ? . r p =5~10m is recommended. 32.768khz crystal recommended capacitor values
rev. 1.30 4? de?e??e? 0?? ?01? rev. 1.30 43 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom t osillat w pw fti the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. 0 qui ? k sta ? t 1 low-powe ? after power on, the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly . however , after the lxt oscillator has fully powered up it can be placed into t he l ow-power m ode b y se tting t he l xtlp b it h igh. t he o scillator wi ll c ontinue t o r un b ut with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it shou ld be no ted t hat, no m atter wha t c ondition t he l xtlp bi t i s se t t o, t he l xt osc illator wi ll always function normally , the only dif ference is that it will take more time to start up if in the low- power mode. the low speed oscillator , in addition to providing a system clock source is also used to provide a c lock so urce t o t wo o ther d evice f unctions. t hese a re t he w atchdog t imer a nd t he t ime b ase interrupts. present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. these d evices h ave t hree d ifferent c lock sou rces fo r b oth t he c pu a nd peripheral fu nction o peration. by providing the user with clock options using register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency , f h , or low frequency , f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock is sourced from the hirc oscillator . the low speed system clock source can be sourced from internal clock f l . if f l is selected then it can be sourced by either the lxt or lirc oscillators, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there is one additional internal clock for the peripheral circuits, the t ime base clock, f tbc . f tbc i s sourced fr om t he l irc o r l xt o scillators. t he f tbc clock i s u sed a s a so urce fo r t he t ime b ase interrupt functions and for the tms.
rev. 1.30 44 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 4? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom hirc p?es?ale? f h lirc low speed os?illato?s f h /? f h /1? f h /?4 f h /8 f h /4 f h /3? hlclk cks?~cks0 ?its f sys f sub high speed os?illato? lxt configu?ation option wdt sleep ti?e base 0 f sys /4 tbck ti?e base 1 f tb f tbc f lirc f lxt f l system clock confgurations note: when the system clock source f is switched to f l from f h , the high speed oscillat or will stop to conserve the power. thus there is no f h ~f h /64 for the peripheral circuit s to use. system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, i dle0 a nd i dle1 m odes a re u sed wh en t he m icrocontroller c pu i s swi tched o ff t o conserve power. operating mode description cpu f sys f sub f tbc f l normal ? ode on f h ~f h / ? 4 on on on slow ? ode on f l on on on idle0 ? ode off off on on off idle1 ? ode off on on on on sleep0 ? ode off off off off off sleep1 ? ode off off on off off
rev. 1.30 44 de?e??e? 0?? ?01? rev. 1.30 4 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom orma m as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the h igh sp eed o scillator hi rc. t he h igh sp eed o scillator wi ll h owever fr st b e d ivided b y a r atio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod regis ter. a lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from the low speed oscillator lirc or lxt . running the micro controller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. the sleep0 mode is entered when an hal t instruction is executed and when the idlen bit in the smod registe r is low . in the sleep0 mode the cpu will be stopped, and the f sub clock will be stopped too, and the w atchdog t imer function is disabled. the sleep1 mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep1 mode the cpu will be stopped. however the f sub clocks will continue to operate if the w atchdog t imer function is enabled. the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is low . in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer and tms. in the idle0 mode, the system oscillator will be stopped. the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode, the w atchdog t imer clock, f sub , will be on.
rev. 1.30 4 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 47 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ctl rist the registers, smod and smo d1, are used for overall control of the internal clocks within the device. na ? e cks ? cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 bit 7 ~ 5 cks2 ~ cks0 : the system clock selection when hlclk is 0 000: f l (f lirc or f lxt ) 001: f l (f lirc or f lxt ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be the lirc or lxt , a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0 bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power-on. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ h /64 or f l clock will be selected. when system clock switches from the f h clock to the l clock and the f h clock will be automatically switched off to conserve power .
rev. 1.30 4? de?e??e? 0?? ?01? rev. 1.30 47 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom mod rist it 6 4 2 0 na ? e fsyson d3 lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x unknown bit 7 fsyson : f control in idle mode 0: disable 1: enable this bit is used to control whether the system clock is switched on or not in the idle mode. if this bit is set to 0, the system clock will be switched off in the idle mode. however, the system clock will be switched on in the idle mode when the fsyson bit is set to 1. bit 6~4 unimplemented, read as 0 bit 3 d3 : reserved bit bit 2 lvrf : lvr function reset fag described elsewhere bit 1 unimplemented, read as 0 bit 0 wrf : wdt control register software reset fag described elsewhere the devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in si mple t erms, mo de swi tching b etween t he nor mal mo de a nd sl ow mo de i s e xecuted using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the smod1 register.
rev. 1.30 48 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 49 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tms.
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rev. 1.30 48 de?e??e? 0?? ?01? rev. 1.30 49 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom orma m t o m withi when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se tting t he hlclk bit to 0 and setting the cks2~cks0 bits to 000 or 001 in the smod register .this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc or lxt oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the l to bit in the smod register. cks?~cks0 = 00xb & hlclk = 0 sleep0 mode idlen=0 halt inst?u?tion is exe?uted sleep1 mode idle0 mode idle1 mode wdt is off idlen=0 halt inst?u?tion is exe?uted wdt is on idlen=1? fsyson=0 halt inst?u?tion is exe?uted idlen=1? fsyson=1 halt inst?u?tion is exe?uted
rev. 1.30 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?1 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom o m t orma m withi in slow mode the system uses lirc or lxt low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. cks2~cks0 000b or 001b as hlclk = 0 or hlclk = 1 sleep0 mode idlen=0 halt instruction is executed sleep1 mode idle0 mode idle1 mode wdt is off idlen=0 halt instruction is executed wdt is on idlen=1, fsyson=0 halt instruction is executed idlen=1, fsyson=1 halt instruction is executed entering the sleep0 mode there is only one way for the devic es to enter the sleep0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.30 ?0 de?e??e? 0?? ?01? rev. 1.30 ? 1 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom eti th eep m there is only one way for the devic es to enter the sleep1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the hal t instruction, but the wdt will remain with the clock source coming from the f lirc clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in smod1 register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruction, but the t ime base clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. there is only one way for the devic es to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in smod1 register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.30 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?3 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ta ct csiatis as the main reason for entering the sleep or idle mode is to keep the current consumption of the devices to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit de signer i f t he powe r c onsumption i s t o be m inimised. spe cial a ttention m ust be m ade t o the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any floating input pins could create internal oscillations and result in increased current consumpti on. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must eit her be set up as out puts or if set up as input s must have pul l-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. t hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if t he sy stem i s wo ken u p b y a n e xternal r eset, t he d evices wi ll e xperience a f ull sy stem r eset, however, if these devices are woken up by a wdt overflow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the halt instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.30 ?? de?e??e? 0?? ?01? rev. 1.30 ? 3 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ath ti the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. the w atchdog t imer clock source is provided by the internal f sub clock whi ch is supplied by the lirc or lx t os cillator. the w atchdog t imer s ource clock is then s ubdivided by a ratio of 2 8 t o 2 15 t o gi ve l onger t imeouts, t he a ctual va lue be ing c hosen usi ng t he w s2~ws0 bi ts i n t he w dtc register. the lxt oscillator is supplied by an external 32.768khz crystal. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v . however , it should be noted that this specifed internal clock period can vary with v dd , tempe rature and process variations. the wdt can be enabled/disabled using the wdtc register. a single register , wdtc, controls the required timeout period as well as the enable/disable operation. the wrf software reset fag will be indicated in the smod1 register . these registers control the overall operation of the w atchdog t imer. na ? e we4 we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function software control 10101: wdt disable 01010: wdt enable other values: reset mcu when thes e bits are changed to any other values by the environmental noise to reset the microcontrolle r, the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit will be set to 1to indicate the reset source. bit 2~0 : wdt t ime-out period selection 000: 2 8 / f sub 001: 2 9 /f sub 010: 2 10 /f sub 011: 2 11 /f sub (default) 100: 2 12 /f sub 101: 2 13 /f sub 110: 2 14 /f sub 111: 2 15 /f sub these three bi ts de termine the di vision rat io of the w atchdog t imer sourece clock, which in turn determines the timeout period.
rev. 1.30 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom mod rist it 6 4 2 0 na ? e fsyson d3 lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x unknown bit 7 fsyson : f control in idle mode described elsewhere bit 6~4 unimplemented, read as 0 bit 3 d3 : reserved bit bit 2 lvrf : lvr function reset fag described elsewhere bit 1 unimplemented, read as 0 bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instructions will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. w ith regard to the w atchdog t imer enable/disable function, there are fve bits, we4~we0, in the wdtc register to additional enable/disable and reset control of the w atchdog t imer. 10101b disa ? le 01010b ena ? le any othe ? value reset mcu wat?hdog ti?e? ena?le/disa?le cont?ol under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. four methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a value other than 01010b and 10101b is written into the we4~we0 bit locations, the second is an external hardware reset, which means a low level on the external reset pin, the third is using the w atchdog t imer software clear instructions and the fourth is via a hal t instruction. there is only one method of using software instruction to clear the watchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time-out period is when the 2 15 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.
rev. 1.30 ?4 de?e??e? 0?? ?01? rev. 1.30 ?? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom clr wdt inst?u?tion 8-stage divide? wdt p?es?ale? we4~we0 ?its wdtc registe? reset mcu f sub /? 8 8-to-1 mux clr ws?~ws0 wdt ti?e-out (? 8 /f sub ~ ? 1? /f sub ) lxt m u x low speed os?illato? configu?ation option halt inst?u?tion lirc f sub wat?hdog ti?e? reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the devices can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in a ddition t o t he p ower-on r eset, si tuations m ay a rise wh ere i t i s n ecessary t o f orcefully a pply a reset condition when the microcontroller is running. one example of this is where after power has be en a pplied a nd t he m icrocontroller i s a lready ru nning, t he res l ine i s fo rcefully pu lled l ow. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. there are several w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally: the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. power-on reset timing chart
rev. 1.30 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?7 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom re pi rst although t he m icrocontroller ha s a n i nternal rc re set func tion, i f t he v dd powe r suppl y ri se t ime is not fas t enough or does not s tabilise quickly at pow er-on, the internal res et function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay , normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up t imer. for most applicat ions a resistor connected between v dd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to t he res p in sho uld b e k ept a s sho rt a s p ossible t o m inimize a ny st ray n oise i nterference. fo r applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. vdd v dd res 10k ? ~ 100k ? 0.01f** 1n4148* vss 0.1f~1f 300 ? * note: * it is recommended that this component is added for added esd protection ** it is recomm ended that this component is added in environments where power line noise is signifcant more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using exter nal hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. inte?nal reset t rstd +t sst res 0.9v dd 0.4v dd res reset ti?ing cha?t
rev. 1.30 ?? de?e??e? 0?? ?01? rev. 1.30 ? 7 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? na ? e rstc7 rstc ? rstc ? rstc4 rstc3 rstc ? rstc1 rstc0 r/w r/w r/w r/w r/w r r r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 0 rstc7 ~ rstc0 : pc2/ res selection 01010101: confgured as pc2 pin or other function 10101010: confgured as res pin other v alues: inhibit to use all reset will reset this register as por value except wdt time out hardware warm reset. the devices both contain a low voltage reset circuit in order to monitor the supply voltage of the device and provide an mcu reset should the value fall below a certain predefned level. the l vr function is always enabled during the normal and slow modes with a specifc l vr voltage v lvr . if the s upply voltage of the device drops to w ithin a range of 0.9v ~v lvr s uch as might occur w hen changing the battery , the l vr w ill automatically reset the devices internally and the l vrf bit in t he smod1 re gister wi ll a lso be set t o1. for a va lid l vr si gnal, a l ow vol tage, i .e., a vol tage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the l vr characteristics. if t he l ow vol tage st ate does not e xceed t his va lue, t he l vr wi ll i gnore t he l ow supply voltage and will not perform a reset function. the actual v lvr is 2.1v , the l vr will reset the device after 2~3 lirc clock cycles. note that the l vr function will be automatically disabled when the device enters the sleep/idle mode. lvr inte?nal reset t rstd + t sst low voltage reset ti?ing cha?t ? na ? e fsyson d3 lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x unknown bit 7 fsyson : f control in idle mode describe elsewhere bit 6~4 unimplemented, read as 0 bit 3 d3 : reserved bit bit 2 lvrf : lvr function reset fag 0: not active 1: active this bit can be clear to 0, but can not be set to 1. bit 1 unimplemented, read as 0 bit 0 wrf : wdt control register software reset fag describe elsewhere
rev. 1.30 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?9 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ath tit rst i al oati the w atchdog tim e-out reset during normal operation is the same as an l vr reset except that the watchdog time-out fag t o will be set to 1. wdt ti?e-out inte?nal reset t rstd + t sst wdt ti?e-out reset du?ing no??al ope?ation ti?ing cha?t wat?hdog ti?e-out reset du?ing sleep o? idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt ti?e-out inte?nal reset t sst wdt ti?e-out reset du?ing sleep o? idle ti?ing cha?t reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: 0 0 powe ? -on ? eset u u lvr ? eset du ? ing normal o ? slow mode ope ? ation 1 u wdt ti ? e-out ? eset du ? ing normal o ? slow mode ope ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? sleep mode ope ? ation note: u stands fo ? un ? hanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs.
rev. 1.30 ?8 de?e??e? 0?? ?01? rev. 1.30 ? 9 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom t citi at reet p ? og ? a ? counte ? reset to ze ? o inte ?? upts all inte ?? upts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins ? ounting ti ? e ? modules ti ? e ? modules will ? e tu ? ned off input/output po ? ts i/o po ? ts will ? e setup as inputs sta ? k pointe ? sta ? k pointe ? will point to the top of the sta ? k the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes h ow e ach t ype o f re set a ffects e ach o f t he m icrocontroller i nternal re gisters. not e t hat where m ore t han one pa ckage t ype e xists t he t able wi ll re fect t he sit uation for t he l arger pa ckage type. mp0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---- -xxx ---- -uuu ---- -uuu ---- -uuu ---- -uuu ---- xxxx ---- uuuu ---- uuuu ---- uuuu ---- uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu smod 000- 0011 000- 0011 000- 0011 000- 0011 uuu- uuuu integ ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu intc ? -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi ? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu wdtc 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 0011 0111 uuuu uuuu smod1 0--- 0x-0 0--- 0x-0 0--- 0x-0 0--- 0x-0 u--- uu-u scomc -000 ---- -000 ---- -000 ---- -000 ---- -uuu ---- sadol (adrfs=0) xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- sadol (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sadoh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
rev. 1.30 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?1 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom rist HT66F0042 ht66f0082 rst pw o dt tit al oati re rst al oati re rst hat dt tit hat sadoh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu sadc0 0000 -000 0000 -000 0000 -000 0000 -000 uuuu -uuu sadc1 000- -000 000- -000 000- -000 000- -000 uuu- -uuu sadc ? 00-- 0000 00-- 0000 00-- 0000 00-- 0000 uu-- uuuu rstc 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu pas0 00-- 0000 00-- 0000 00-- 0000 00-- 0000 uu-- uuuu pas1 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu pbs0 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu pbs1 --00 00-- --00 00-- --00 00-- --00 00-- --uu uu-- ptm0c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm0dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm0dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm0al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm0ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm0rpl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm0rph ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm1c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptm1c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm1al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm1rpl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm1rph ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu pb -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu pbc -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu pbpu -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu pc -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu pcc -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu pcpu -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu eea ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pcs0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pcs1 ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu ifs ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu sledc0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu sledc1 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu ptm ? c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptm ? c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.30 ?0 de?e??e? 0?? ?01? rev. 1.30 ? 1 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom rist HT66F0042 ht66f0082 rst pw o dt tit al oati re rst al oati re rst hat dt tit hat ptm ? dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm ? al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm ? rpl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm ? rph ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm3c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- ptm3c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm3dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm3dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm3al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm3ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ptm3rpl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ptm3rph ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ctm0c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ctm0al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ctm1c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm1c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm1dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm1dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ctm1al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm1ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu simc0 111- 0000 111- 0000 111- 0000 111- 0000 uuu- uuuu simc1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu simc ? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu sima 0000 000- 0000 000- 0000 000- 0000 000- uuuu uuu- simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu simtoc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pd ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu pdc ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu pdpu ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu pds0 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu usr 0000 1011 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr ? 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu txr_rxr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu note: * stands for warm reset - not implement u stands for unchanged x stands for unknown
rev. 1.30 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?3 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom t/ott pts holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the de vices pro vide bi directional i nput/output l ines l abeled wi th por t na mes p a~pd. t hese i/ o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. ht ?? f004 ? ht ?? f008 ? pa pa7 pa ? pa ? pa4 pa3 pa ? pa1 pa0 pac pac7 pac ? pac ? pac4 pac3 pac ? pac1 pac0 papu papu7 papu ? papu ? papu4 papu3 papu ? papu1 papu0 pawu pawu7 pawu ? pawu ? pawu4 pawu3 pawu ? pawu1 pawu0 pb pb ? pb ? pb4 pb3 pb ? pb1 pb0 pbc pbc ? pbc ? pbc4 pbc3 pbc ? pbc1 pbc0 pbpu pbpu ? pbpu ? pbpu4 pbpu3 pbpu ? pbpu1 pbpu0 pc pc ? pc ? pc4 pc3 pc ? pc1 pc0 pcc pcc ? pcc ? pcc4 pcc3 pcc ? pcc1 pcc0 pcpu pcpu ? pcpu ? pcpu4 pcpu3 pcpu ? pcpu1 pcpu0 ht ?? f008 ? pd pd3 pd ? pd1 pd0 pdc pdc3 pdc ? pdc1 pdc0 pdpu pdpu3 pdpu ? pdpu1 pdpu0 i/o registe? list : unimplemented, read as 0 pawun : wake-up function control 0: disable 1: enable pan/pbn/pcn/pdn : i/o data bit 0: data 0 1: data 1 pacn/pbcn/pccn/pdcn : i/o type selection 0: output 1: input papun/pbpun/pcpun/pdpun : pull-high function control 0: disable 1: enable many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using register papu~pdpu, and are implemented using weak pmos transistors.
rev. 1.30 ?? de?e??e? 0?? ?01? rev. 1.30 ? 3 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pt a a the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. each i/o port has its ow n control register known as p ac~pdc, to control the input/output configuration. w ith t hese c ontrol re gisters, e ach cmos out put or i nput c an be re configured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established w here more than one pin function is selected simultaneous ly. each device includes output f unction se lection r egisters px sn a nd i nput f unction se lection r egister i fs f or se lecting t he desired functions of the multi-function pin-shared pins. the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. pas0 pas07 pas0 ? pas03 pas0 ? pas01 pas00 pas1 pas1 ? pas14 pas13 pas1 ? pas11 pas10 pbs0 pbs0 ? pbs04 pbs03 pbs0 ? pbs01 pbs00 pbs1 pbs1 ? pbs14 pbs13 pbs1 ? pcs0 pcs07 pcs0 ? pcs0 ? pcs04 pcs03 pcs0 ? pcs01 pcs00 pcs1 (ht ?? f004 ? ) pcs11 pcs10 pcs1 (ht ?? f008 ? ) pcs1 ? pcs14 pcs13 pcs1 ? pcs11 pcs10 pds0 (ht ?? f008 ? ) pds03 pds0 ? pds01 pds00 ifs (ht ?? f004 ? ) ptp ? ips ptck3ps ptck ? ps ctck1ps ifs (ht ?? f008 ? ) ptp3ips ptp0ips ptck1ps ctck0ps ptp ? ips ptck3ps ptck ? ps ctck1ps pin-sha?ed fun?tion sele?tion registe? list
rev. 1.30 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? na ? e pas07 pas0 ? pas03 pas0 ? pas01 pas00 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 pas07~pas06 : pa3 pin-shared control bits 00: pa3 01: ctp1 10: pa3 11: scom0 bit 5~4 unimplemented, read as 0 bit 3~2 pas03~pas02 : pa1pin-shared control bits 00: pa1 01: ptp0 10: pa1 11: an7 bit 1~0 pas01~pas00 : pa0 pin-shared control bits 00: pa0/ptp0i_0 01: pa0/ptp0i_0 10: pa0/ptp0i_0 11: an6 ? na ? e pas1 ? pas14 pas13 pas1 ? pas11 pas10 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~4 pas15~pas14 : pa6 pin-shared control bits 00: pa6 01: sck/scl 10: pa6 11: an5 bit 3~2 pas13~pas12 : pa5 pin-shared control bits 00: pa5/ptck2_0 01: sdo 10: pa5/ptck2_0 11: an4 bit 1~0 pas11~pas10 : pa4 pin-shared control bits 00: pa4 01: sdi/sda 10: pa4 11: an3
rev. 1.30 ?4 de?e??e? 0?? ?01? rev. 1.30 ?? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? na ? e pbs0 ? pbs04 pbs03 pbs0 ? pbs01 pbs00 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~4 pbs05~pbs04 : pb2 pin-shared control bits 00: pb2/ptck3_0/int1 01: pb2/ptck3_0/int1 10: pb2/ptck3_0/int1 11: an2 bit 3~2 pbs03~pbs02 : pb1 pin-shared control bits 00: pb1/ptp3i_0 01: scs 10: vrefo 11: an1 bit 1~0 pbs01~pbs00 : pb0 pin-shared control bits 00: pb0/ptp1i/int0 01: pb0/ptp1i/int0 10: vref 11: an0 ? na ? e pbs1 ? pbs14 pbs13 pbs1 ? r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~4 pbs15~pbs14 : pb6 pin-shared control bits 00: pb6 01: ptp2 10: pb6 11: scom2 bit 3~2 pbs13~pbs12 : pb5 pin-shared control bits 00: pb5 01: ptp3 10: pb5 11: scom3 bit 1~0 unimplemented, read as 0
rev. 1.30 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?7 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? na ? e pcs07 pcs0 ? pcs0 ? pcs04 pcs03 pcs0 ? pcs01 pcs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pcs07~pcs06 : pc3 pin-shared control bits 00: pc3/ptp2i_1 01: pc3/ptp2i_1 10: pc3/ptp2i_1 11: scom2 bit 5~4 pcs05~pcs04 : pc2 pin-shared control bits 00: pc2 01: pc2 10: pc2 11: ctp0 note: these bits are valid when rstc[7:0]=01010101 bit 3~2 pcs03~pcs02 : pc1 pin-shared control bits 00: pc1/ptck0 01: pc1/ptck0 10: pc1/ptck0 11: scom1 bit 1~0 pcs01~pcs00 : pc0 pin-shared control bits 00: pc0 01: pc0 10: pc0 11: ptp1 ? na ? e pcs11 pcs10 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 pcs11~pcs10 : pc4 pin-shared control bits 00: pc4/ctck1_1 01: pc4/ctck1_1 10: pc4/ctck1_1 11: scom3
rev. 1.30 ?? de?e??e? 0?? ?01? rev. 1.30 ? 7 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? na ? e pcs1 ? pcs14 pcs13 pcs1 ? pcs11 pcs10 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~4 pcs15~pcs14 : pc6 pin-shared control bits 00: pc6/ptck2_1 01: tx 10: pc6/ptck2_1 11: pc6/ptck2_1 bit 3~2 pcs13~pcs12 : pc5 pin-shared control bits 00: pc5/ptck3_1 01: rx 10: pc5/ptck3_1 11: pc5/ptck3_1 bit 1~0 pcs11~pcs10 : pc4 pin-shared control bits 00: pc4/ctck1_1 01: pc4/ctck1_1 10: pc4/ctck1_1 11: scom3 ? na ? e pds03 pds0 ? pds01 pds00 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 pds03~pds02 : pd1 pin-shared control bits 00: pd1/ptp0i_1 01: pd1/ptp0i_1 10: pd1/ptp0i_1 11: scom1 bit 1~0 pds01~pds00 : pd0 pin-shared control bits 00: pd0/ctck0_1 01: pd0/ctck0_1 10: pd0/ctck0_1 11: scom0
rev. 1.30 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 ?9 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? na ? e ptp ? ips ptck3ps ptck ? ps ctck1ps r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 ptp2ips : ptp2i pin remapping control bit 0: ptp2i_0 on pa7(default) 1: ptp2i_1 on pc3 bit 2 ptck3ps : ptck3 pin remapping control bit 0: ptck3_0 on pb2(default) 1: ptck3_1 on pc5 bit 1 ptck2ps : ptck2 pin remapping control bit 0: ptck2_0 on pa5(default) 1: ptck2_1 on pc6 bit 0 ctck1ps : ctck1 pin remapping control bit 0: ctck1_0 on pb3(default) 1: ctck1_1 on pc4 ? na ? e ptp3ips ptp0ips ptck1ps ctck0ps ptp ? ips ptck3ps ptck ? ps ctck1ps r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ptp3ips : ptp3i pin remapping control bit 0: ptp3i_0 on pb1(default) 1: ptp3i_1 on pd2 bit 6 ptp0ips : ptp0i pin remapping control bit 0: ptp0i_0 on pa0(default) 1: ptp0i_1 on pd1 bit 5 ptck1ps : ptck1 pin remapping control bit 0: ptck1_0 on pb4(default) 1: ptck1_1 on pd3 bit 4 ctck0ps : ctck0 pin remapping control bit 0: ctck0_0 on pa2(default) 1: ctck0_1 on pd0 bit 3 ptp2ips : ptp2i pin remapping control bit 0: ptp2i_0 on pa7(default) 1: ptp2i_1 on pc3 bit 2 ptck3ps : ptck3 pin remapping control bit 0: ptck3_0 on pb2(default) 1: ptck3_1 on pc5 bit 1 ptck2ps : ptck2 pin remapping control bit 0: ptck2_0 on pa5(default) 1: ptck2_1 on pc6 bit 0 ctck1ps : ctck1 pin remapping control bit 0: ctck1_0 on pb3(default) 1: ctck1_1 on pc4
rev. 1.30 ?8 de?e??e? 0?? ?01? rev. 1.30 ? 9 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom /o pt ct ctl the devices support dif ferent source current driving capability for each i/o port. w ith the corresponding selection register , sledc0 and sledc1, each i/o port can support four levels of the source current driving capability . users should refer to the d.c. charac teristics section to select the desired source current for different applications. sledc0 pbps3 pbps ? pbps1 pbps0 paps3 paps ? paps1 paps0 sledc1 (ht ?? f004 ? ) pcps3 pcps ? pcps1 pcps0 sledc1 (ht ?? f008 ? ) pdps1 pdps0 pcps3 pcps ? pcps1 pcps0 i/o po?t sou??e cu??ent cont?ol registe?s list sledc0 registe? bit 7 ? ? 4 3 ? 1 0 na ? e pbps3 pbps ? pbps1 pbps0 paps3 paps ? paps1 paps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pbps3~pbp2 : pb6~pb4 source current selection 00: source current = level 0 (default) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 5~4 pbps1~pbp0 : pb3~pb0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 3~2 paps3~pap2 : pa7~pa4 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 1~0 paps1~pap0 : pa3~pa0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) refer to the d.c. characteristics table for the source current value of each level.
rev. 1.30 70 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 71 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom edc rist HT66F0042 it 6 4 2 0 na ? e pcps3 pcps ? pcps1 pcps0 r/w r/w r/w r/w r/w por 0 1 0 1 bit 7~4 unimplemented, read as 0 bit 3~2 pcps3~pcps2 : pc6~pc4 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 1~0 pcps1~pcps0 : pc3~pc0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) refer to the d.c. characteristics table for the source current value of each level. na ? e pdps1 pdps0 pcps3 pcps ? pcps1 pcps0 r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 bit 7~6 unimplemented, read as 0 bit 5~4 pdps1~pdps0 : pd3~pd0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 3~2 pcps3~pcps2 : pc6~pc4 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 1~0 pcps1~pcps0 : pc3~pc0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) refer to the d.c. characteristics table for the source current value of each level.
rev. 1.30 70 de?e??e? 0?? ?01? rev. 1.30 71 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom /o pi tts the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ? ? ? ?? generic input/output structure

? ?
? ? ? ? - ? ? - ? ? ? ? a/d input/output structure
rev. 1.30 7 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 73 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pai csiatis within the user program, one of the frs t things to consider is port initialisation. after a res et, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input stat e, the level of whi ch de pends on the other connected circuitry and whe ther pull - high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data regis ters are frst programmed. selecting which pins are inputs and which are outputs can be achieved byt e-wide by l oading t he c orrect va lues i nto t he a ppropriate port c ontrol re gister or by programming i ndividual bi ts i n t he port c ontrol re gister usi ng t he set [m ].i a nd clr [m ].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. one of the most fundamental functions in any microcont roller device is the ability to control and measure time. t o implement time related functions the devices include several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact and periodic tm sections. each of the devices contains sixtms. each individual tm can be categorised as a certain type, namely compact t ype tm or periodic t ype tm. although similar in nature, the dif ferent tm types vary in their feature complexity . the common features to the compact and periodic tms will be described in this section and the detailed operation will be described in corresponding sections. the main features and dif ferences between the two types of tms are summarised in the accompanying table. ti ? e ? /counte ? i/p captu ? e co ? pa ? e mat ? h output pwm channels 1 1 single pulse output 1 pwm align ? ent edge edge pwm adjust ? ent pe ? iod & duty duty o ? pe ? iod duty o ? pe ? iod tm fun?tion su??a?y
rev. 1.30 7? de?e??e? 0?? ?01? rev. 1.30 73 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ctm ptm 10- ? it ctm0 10- ? it ctm1 10- ? it ptm0 10- ? it ptm1 10- ? it ptm ? 10- ? it ptm3 tm type refe?en?e tm ope?ation the t wo d ifferent t ypes o f t ms o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the xtnck2~xtnck0 bits in the xtmnc0 c ontrol re gisters. t he c lock sourc e c an be a ra tio of e ither t he syst em c lock f sys or t he internal high clock f h , the f tbc clock source or the external xtckn pin. the xtckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. the compact and periodic type tms each has two internal interrupts, the internal comparator a or com parator p , whi ch ge nerate a tm interrupt when a com pare match condition oc curs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. each of the tms, irrespective of what type, has two tm input pins, with the label xtckn and xtpni. the tm input pin xtckn, is essentially a clock source for the tm and is selected using the xtnck2~xtnck0 bits in the xtmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the xtnck2~xtnck0 bits and the pin-shared register. the tm input pin can be chosen to have either a rising or falling active edge. the other ptm input pin, ptpni, is the capture input pin whose active edge can be a rising edge, a falling edge or both rising and fallin g edges and the active edge transit ion type is selected using the ptnio1 and ptnio0 bits in the ptmnc1 register. the tms each have one output pin with the label xtpn. when the tm is in the compare match output mode, the pin can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external xtpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be selected and setup using registers. the bits in one of the pin-shared registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function.
rev. 1.30 74 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 7? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom some tm input pin names have a _0 or _1 suffx. pin names that include a _1 suffx indicate that the tm input has another remapping pin. the pin remapping function is controlled using the bits in the ifs registers. ht ?? f004 ? input ctck0_0 ctck1_0/ctck1_1 output ctp0 ctp1 ht ?? f008 ? input ctck0_0/ctck0_1 ctck1_0/ctck1_1 output ctp0 ctp1 ctmn input/output pins devi?e pins ptm0 ptm1 ptm? ptm3 ht ?? f004 ? input ptck0 ptp0i_0 ptck1_0 ptp1i ptck ? _0/ptck ? _1 ptp ? i_0/ptp ? i_1 ptck3_0/ptck3_1 ptp3i_0 output ptp0 ptp1 ptp ? ptp3 ht ?? f008 ? input ptck0 ptp0i_0/ptp0i_1 ptck1_0/ptck1_1 ptp1i ptck ? _0/ptck ? _1 ptp ? i_0/ptp ? i_1 ptck3_0/ptck3_1 ptp3i_0/ptp3i_1 output ptp0 ptp1 ptp ? ptp3 ptmn input/output pins tm input/output pin cont?ol registe? selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , w ith a s ingle bit in each register corres ponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the pin-shared function section. the tm counter registers and the capture/compare ccra register , and ccrp register pair for periodic t imer module, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing the register is carried out ccrp low byte register using the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values.
rev. 1.30 74 de?e??e? 0?? ?01? rev. 1.30 7 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom data bus 8-?it buffe? xtmndh xtmndl ptmnrph ptmnrpl xtmnah xtmnal xtmn counte? registe? (read only) xtmn ccra registe? (read/w?ite) ptmn ccrp registe? (read/w?ite) the following steps show the read and write procedures: ? writing data to ccra or ptm ccrp ? step 1. w rite data to low byte ctmnal, ptmnal or ptmnrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte ctmnah, ptmnah or ptmnrph C here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ptmn ccrp ? step 1. read data from the high byte ctmndh, ctmnah,ptmndh, ptmnah or ptmnrph C here d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte ctmndl, ctmnal, ptmndl, ptmnal or ptmnrpl C this step reads data from the 8-bit buffer.
rev. 1.30 7 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 77 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom cat t tm ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, t imer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one external output pin. ht ?? f004 ? 10- ? it ctm0 10- ? it ctm1 ctck0_0 ctck1_0/ctck1_1 ctp0 ctp1 ht ?? f008 ? 10- ? it ctm0 10- ? it ctm1 ctck0_0/ctck0_1 ctck1_0/ctck1_1 ctp0 ctp1
?? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ?
? ?

? - ?
? ? ? ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ? compact type tm block diagram (n=0~1) compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear t he c ounter by c hanging t he ct non bi t from l ow t o hi gh. t he c ounter wi ll a lso be c leared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers. overall ope ration of e ach com pact t m i s c ontrolled usi ng se veral re gisters. a re ad onl y re gister pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits.
rev. 1.30 7? de?e??e? 0?? ?01? rev. 1.30 77 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom rist a it 6 4 2 0 ctmnc0 ctnpau ctnck ? ctnck1 ctnck0 ctnon ctnrp ? ctnrp1 ctnrp0 ctmnc1 ctnm1 ctnm0 ctnio1 ctnio0 ctnoc ctnpol ctndpx ctncclr ctmndl d7 d ? d ? d4 d3 d ? d1 d0 ctmndh d9 d8 ctmnal d7 d ? d ? d4 d3 d ? d1 d0 ctmnah d9 d8 co?pa?t tm registe? list (n=0~1) ctmnc0 registe? bit 7 ? ? 4 3 ? 1 0 na ? e ctnpau ctnck ? ctnck1 ctnck0 ctnon ctnrp ? ctnrp1 ctnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ctnpau : ctmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6 ~ 4 ctnck2 ~ ctnck0 : select ctmn counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: ctckn_0/ctckn_1 rising edge clock 111: ctckn_0/ctckn_1 falling edge clock these three bits are used to select the clock source for the ctm. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 ctnon : ctmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the ctm. setting the bit high enables the c ounter t o run, c learing t he bi t di sables t he ct m. cl earing t his bi t t o z ero wi ll stop the counter from counting and turn of f the ctm w hich w ill reduce its pow er consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter wi ll r etain i ts r esidual v alue. i f t he c tm i s i n t he c ompare ma tch ou tput mode o r t he pw m o utput mo de t hen t he c tm o utput p in wi ll b e r eset t o i ts i nitial condition, as specifed by the ctnoc bit, when the ctnon bit changes from low to high.
rev. 1.30 78 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 79 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom bit 2 ~ 0 : comparator p match period (ctmn ccrp 3-bit register, compared with the ctmn counter bit 9~bit 7) 000: 1024 ctmn clocks 001: 128 ctmn clocks 010: 256 ctmn clocks 011: 384 ctmn clocks 100: 512 ctmn clocks 101: 640 ctmn clocks 110: 768 ctmn clocks 111: 896 ctmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the ctncclr bit is set to zero. setting the ctncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. ctmnc1 register bit 7 6 5 4 3 2 1 0 na ? e ctnm1 ctnm0 ctnio1 ctnio0 ctnoc ctnpol ctndpx ctncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit7 ~ 6 : select ctmn operating mode 00: compare match output mode 01: undefned 10: pwm output mode 11: t imer/counter mode these b its se tup t he r equired o perating m ode f or t he c tm. t o e nsure r eliable operation the ctm should be switched off before any changes are made to the ctnm1 and ctnm0 bits. in the t imer/counter mode, the ctm output pin state is undefned. bit5 ~ 4 : select ctmn function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the ctm output pin changes stat e whe n a certain condition is reached. the function that these bits select depends upon in which mode the ctm is running. in the compare match output mode, the ctnio1 and ctnio0 bits determine how the ctm output pin changes state when a compare match o ccurs f rom t he c omparator a. t he c tm o utput p in c an b e se tup t o swi tch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. t he i nitial va lue of t he ct m ou tput pi n shou ld be se tup usi ng t he ct noc bit in the ctmnc1 register . note that the output level requested by the ctnio1 and ctnio0 bits must be dif ferent from the initial value setup using the ctnoc bit
rev. 1.30 78 de?e??e? 0?? ?01? rev. 1.30 79 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom otherwise no change will occur on the ctm output pin when a compare match occurs. after the ctm output pin changes state it can be reset to its initial level by changing the level of the ctnon bit from low to high. in the pwm output mode, the ctnio1 and ctnio0 bits determine how the ctm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to only change the values of the ctnio1 and ctnio0 bits only after the ctmn has been switched of f. unpredictable pwm outputs will occur if the ctnio1 and ctnio0 bits are changed when the ctm is running. bit3 : ctpn output control compare match output mode 0: initial low 1: initial high pwm output mode 0: active low 1: active high this is the output control bit for the ctm output pin. its operation depends upon whether ctm is being used in the compare match output mode or in the pwm output mode. it has no ef fect if the ctm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the ctm output pin before a compare match occurs. in the pwm output mode it determin es if the pwm signal is active high or active low. bit2 : ctpn output polarity control 0: non-invert 1: invert this bit controls the polarity of the ctpn output. when the bit is set high the ctm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the ctm is in the t imer/counter mode. bit1 : ctmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit0 : select ctmn counter clear condition 0: ctmn comparator p match 1: ctmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact ctm contains two compa rators, comparator a and compara tor p , either of which can be selected to clear the internal counter . w ith the ctncclr bi t set hi gh, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ctncclr bit is not used in the pwm output mode.
rev. 1.30 80 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 81 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ctmd rist it 6 4 2 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7 ~ 0 d7~d0 : ctmn counter low byte register bit 7 ~ bit 0 ctmn 10-bit counter bit 7 ~ bit 0 na ? e d9 d8 r/w r r por 0 0 bit 7 ~ 2 unimplemented, read as 0 bit 1 ~ 0 d9~d8 : ctmn counter high byte register bit 1 ~ bit 0 ctmn 10-bit counter bit 9 ~ bit 8 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 d7~d0 : ctmn ccra low byte register bit 7 ~ bit 0 ctmn 10-bit ccra bit 7 ~ bit 0 na ? e d9 d8 r/w r/w r/w por 0 0 bit 7 ~ 2 unimplemented, read as 0 bit 1 ~ 0 d9~d8 : ctmn ccra high byte register bit 1 ~ bit 0 ctmn 10-bit ccra bit 9 ~ bit 8
rev. 1.30 80 de?e??e? 0?? ?01? rev. 1.30 81 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom cat t tm oati ms the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm output mode or t imer/counter mode. the operating mode is selected using the ctnm1 and ctnm0 bits in the ctmnc1 register. to select this mode, bits ctnm1 and ctnm0 in the ctmnc1 register , should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from c omparator p . w hen t he c tncclr b it i s l ow, t here a re t wo wa ys i n wh ich t he c ounter c an be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both ctmanf and ctmpnf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the ctncclr bit in the ctmnc1 register is high then the counter will be cleared when a compare match occurs from com parator a. however , here onl y the ctmanf interrupt request fag wil l be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ctncclr is high no ctmpnf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ctmanf interrupt request fag will not be generated. as the name of the mode s uggests, after a comparis on is made, the ctm output pin w ill change state. the ctm output pin condition however only changes state when a ctmanf interrupt request fag is generated after a compare match occurs from comparator a. the ctmpnf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the ctm output pin. the way in which the ctm output pin changes state are determined by the condition of the ctnio1 and ctnio0 bits in the ctmnc1 register . the ctm output pin can be selected using the ctnio1 and ctnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the ctmn output pin, which is setup afte r the ctnon bit changes from low to high, is setup using the ctnoc bit. note that if the ctnio1 and ctnio0 bits are zero then no pin change will take place.
rev. 1.30 8 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 83 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom counte? value 0x3ff ccrp ccra ctnon ctnpau ctnpol ccrp int. flag ctmpnf ccra int. flag ctmanf ctmn o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t ctncclr = 0 ctnm [1:0] = 00 output pin set to initial level low if ctnoc=0 output toggle with ctmanf flag note ctnio [1:0] = 10 a?tive high output sele?t he?e ctnio [1:0] = 11 toggle output sele?t output not affe?ted ?y ctmanf flag. re?ains high until ?eset ?y ctnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctnpol is high co?pa?e mat?h output mode C ctncclr = 0 (n=0~1) note: 1. w ith ctncclr = 0, a comparator p match will clear the counter 2. the tm output pin controlled only by the ctmanf fag 3. the output pin reset to initial state by a ctnon bit rising edge
rev. 1.30 8? de?e??e? 0?? ?01? rev. 1.30 83 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom counte? value 0x3ff ccrp ccra ctnon ctnpau ctnpol ctmn o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t output pin set to initial level low if ctnoc=0 output toggle with ctmanf flag note ctnio [1:0] = 10 a?tive high output sele?t he?e ctnio [1:0] = 11 toggle output sele?t output not affe?ted ?y ctmanf flag. re?ains high until ?eset ?y ctnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctnpol is high ctmpnf not gene?ated no ctmanf flag gene?ated on ccra ove?flow output does not ?hange ctncclr = 1 ctnm [1:0] = 00 ccra int. flag ctmanf ccrp int. flag ctmpnf co?pa?e mat?h output mode C ctncclr = 1 (n=0~1) note: 1. w ith ctncclr = 1, a comparator a match will clear the counter 2. the ctm output pin controlled only by the ctmanf fag 3. the output pin reset to initial state by a ctnon rising edge 4. the ctmpnf fag is not generated when ctncclr = 1
rev. 1.30 84 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 8? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ti/ct m to se lect t his m ode, bi ts ct nm1 a nd ct nm0 i n t he ct mnc1 regi ster shoul d be se t t o 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the ctm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. to select this mode, bits ctnm1 and ctnm0 in the ctmnc1 register should be set to 10 respectively. the pwm function within the ctm is useful for applicat ions which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency b ut o f v arying d uty c ycle o n t he c tm o utput p in, a squ are wa ve ac wa veform c an b e generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extre mely fexible. in the pwm output mode, the ctncclr bit has no ef fect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or dut y c ycle i s de termined usi ng t he ct ndpx bi t i n t he ct mnc1 re gister. t he pw m waveform f requency a nd d uty c ycle c an t herefore b e c ontrolled b y t he v alues i n t he c cra a nd ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the ctnoc bit in the ctmnc1 register is used to select the required polarity of the pwm waveform while the two ctnio1 and ctnio0 bits are used to enable the pwm output or to force the ctm output pin to a fxed high or low level. the ctnpol bit is used to reverse the polarity of the pwm output waveform. ? pe ? iod 1 ? 8 ??? 384 ? 1 ? ? 40 7 ? 8 89 ? 10 ? 4 duty ccra if f sys = 16mhz, ctm clock source is f sys /4, ccrp = 100b, ccra =128, the ctm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? pe ? iod ccra duty 1 ? 8 ??? 384 ? 1 ? ? 40 7 ? 8 89 ? 10 ? 4 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.30 84 de?e??e? 0?? ?01? rev. 1.30 8 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom counte? value ccrp ccra ctnon ctnpau ctnpol ctmn o/p pin (ctnoc=1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if ctnon ?it low counte? reset when ctnon ?etu?ns high pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctnpol = 1 pwm pe?iod set ?y ccrp ctmn o/p pin (ctnoc=0) ccra int. flag ctmanf ccrp int. flag ctmpnf ctndpx = 0 ctnm [1:0] = 10 pwm mode C ctndpx = 0 (n=0~1) note: 1. here ctndpx = 0 - counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues running even when ctnio[1:0] = 00 or 01 4. the ctncclr bit has no infuence on pwm operation
rev. 1.30 8 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 87 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom counte? value ccrp ccra ctnon ctnpau ctnpol ccrp int. flag ctmpnf ccra int. flag ctmanf ctmn o/p pin (ctnoc=1) ti?e counte? ?lea?ed ?y ccra pause resu?e counte? stop if ctnon ?it low counte? reset when ctnon ?etu?ns high pwm duty cy?le set ?y ccrp pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctnpol = 1 pwm pe?iod set ?y ccra ctmn o/p pin (ctnoc=0) ctndpx = 0 ctnm [1:0] = 10 pwm mode C ctndpx = 1 (n=0~1) note: 1. here ctndpx = 1 - counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when ctnio[1:0] = 00 or 01 4. the ctncclr bit has no infuence on pwm operation
rev. 1.30 8? de?e??e? 0?? ?01? rev. 1.30 87 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pii t tm ptm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can also be controlled with two external input pins and can drive one external output pin. ht ?? f004 ? 10- ? it ptm0 10- ? it ptm1 10- ? it ptm ? 10- ? it ptm3 ptck0 ? ptp0i_0 ptck1_0 ? ptp1i ptck ? _0/ptck ? _1 ? ptp ? i_0/ptp ? i_1 ptck3_0/ptck3_1 ? ptp3i_0 ptp0 ptp1 ptp ? ptp3 ht ?? f008 ? 10- ? it ptm0 10- ? it ptm1 10- ? it ptm ? 10- ? it ptm3 ptck0 ? ptp0i_0/ptp0i_1 ptck1_0/ptck1_1 ? ptp1i ptck ? _0/ptck ? _1 ? ptp ? i_0/ptp ? i_1 ptck3_0/ptck3_1 ? ptp3i_0/ptp3i_1 ptp0 ptp1 ptp ? ptp3 pe?iodi? tm ope?ation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with the ccra and ccrp registers. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the ptnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pin. all operating setup conditions are selected using relevant internal registers.
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rev. 1.30 88 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 89 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pii t tm rist dsiti overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrp value. the remaining two registers are control registers which setup the different operating and control modes. ptmnc0 ptnpau ptnck ? ptnck1 ptnck0 ptnon ptmnc1 ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr ptmndl d7 d ? d ? d4 d3 d ? d1 d0 ptmndh d9 d8 ptmnal d7 d ? d ? d4 d3 d ? d1 d0 ptmnah d9 d8 ptmnrpl d7 d ? d ? d4 d3 d ? d1 d0 ptmnrph d9 d8 10-?it pe?iodi? tm registe? list (n=0~3) ptmnc0 registe? bit 7 ? ? 4 3 ? 1 0 na ? e ptnpau ptnck ? ptnck1 ptnck0 ptnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ptnpau : ptmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 ptnck2~ptnck0 : select ptmn counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: ptckn_0/ptckn_1 rising edge clock 111: ptckn_0/ptckn_1 falling edge clock these three bits are used to select the clock source for the ptm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f tbc is another internal clock, the details of which can be found in the oscillator section.
rev. 1.30 88 de?e??e? 0?? ?01? rev. 1.30 89 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom bit 3 : ptmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the ptm is in the compare match output mode or the pwm output mode or single pulse output mode then the ptm output pin will be reset to its initial condition, as specifed by the ptnoc bit, when the ptnon bit changes from low to high. bit 2~0 unimplemented, read as 0 ptmnc1 register bit 7 6 5 4 3 2 1 0 na ? e ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : select ptmn operation mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the ptm. t o ensure reliable operation the tm should be switched of f before any changes are made to the ptnm1 and ptnm0 bits. in the t imer/counter mode, the ptm output pin state is undefned. bit 5~4 : select ptmn output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode /single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of the selected ptmn input pin 01: input capture at falling edge of the selected ptmn input pin 10: input capture at falling/rising edge of the selected ptmn input pin 11: input capture disabled timer/counter mode unused these two bits are used to determine how the ptm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.30 90 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 91 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom in the compare match output mode, the ptnio1 and ptnio0 bits determine how the ptm output pin changes state when a compare match occurs from the comparator a. the pt m out put pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pre sent state when a compare match occurs from the comparator a. when these bits are both zero, then no change will take place on the output. the initial value of the ptm output pin should be setup using the ptnoc bit. note that the output level requested by the pt nio1 a nd pt nio0 b its m ust b e d ifferent f rom t he i nitial v alue se tup u sing t he ptnoc bit otherwise no change will occur on the ptm output pin when a compare match occurs. after the ptm output pin changes state, it can be reset to its initial level by changing the level of the ptnon bit from low to high. in the pwm mode, the ptnio1 and ptnio0 bits determine how the ptm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the ptnio1 and ptnio0 bits only after the ptm has been switched of f. unpredictable pwm outputs will occur if the ptnio1 and ptnio0 bits are changed when the ptm is running. bit 3 : ptpn output control bit compare match output mode 0: initial low 1: initial high pwm output mode / single pulse output mode 0: active low 1: active high this is the output control bit for the ptm output pin. its operation depends upon whether pt m i s b eing u sed i n t he c ompare ma tch ou tput mo de o r i n t he pw m mode/single pulse output mode. it has no ef fect if the ptm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the ptm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 : ptpn output polarity control 0: non-invert 1: invert this bit controls the polarity of the ptpn output pin. when the bit is set high the ptm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the ptm is in the t imer/counter mode. bit 1 : ptmn capture trigger source select 0: from ptpni_0/ptpni_1 1: from ptckn_0/ptckn_1 bit 0 : select ptmn counter clear condition 0: ptmn comparatror p match 1: ptmn comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the ptncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ptncclr bit is not used in the pwm, single pulse or input capture mode.
rev. 1.30 90 de?e??e? 0?? ?01? rev. 1.30 91 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ptmd rist it 6 4 2 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 ptmndl : ptmn counter low byte register bit 7 ~ bit 0 ptmn 10-bit counter bit 7 ~ bit 0 na ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ptmndh : ptmn counter high byte register bit 1 ~ bit 0 ptmn 10-bit counter bit 9 ~ bit 8 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ptmnal : ptmn ccra low byte register bit 7 ~ bit 0 ptmn 10-bit ccra bit 7 ~ bit 0 na ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ptmnah : ptmn ccra high byte register bit 1 ~ bit 0 ptmn 10-bit ccra bit 9 ~ bit 8 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ptmnrpl : ptmn ccrp low byte register bit 7 ~ bit 0 ptmn 10-bit ccrp bit 7 ~ bit 0
rev. 1.30 9 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 93 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ptmrph rist it 6 4 2 0 na ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 ptmnrph : ptmn ccrp high byte register bit 1 ~ bit 0 ptmn 10-bit ccrp bit 9 ~ bit 8 the periodic t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the ptnm1 and ptnm0 bits in the ptmnc1 register. to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register , should be all cleared to 00 r espectively. i n t his m ode o nce t he c ounter i s e nabled a nd r unning i t c an b e c leared b y t hree methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the ptncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are a ll z ero whi ch a llows t he c ounter t o o verfow. he re b oth t he pt manf a nd pt mpnf i nterrupt request fags for comparator aand comparator p respectively, will both be generated. if the ptncclr bit in the ptmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the ptmanf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ptncclr is high no ptmpnf interrupt request flag will be generated. in the compare match output mode, the ccra can not be set to 0. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ptmanf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a ptmanf interrupt request fag is generated after a compare match occurs from comparator a. the ptmpnf interrupt request fag, generated from a compare match from comparator p , will have no ef fect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the ptnio1 and ptnio0 bits in the ptm nc1 register . the tm output pin can be selected using the ptnio1 and ptnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the ptnon bi t changes from low to hi gh, is setup using the ptnoc bi t. note tha t if the ptnio1, ptnio0 bits are zero then no pin change will take place.
rev. 1.30 9? de?e??e? 0?? ?01? rev. 1.30 93 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom counte? value 0x3ff ccrp ccra pton ptpau ptpol ccrp int. flag ptmpnf ccra int. flag ptmanf ptm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t output pin set to initial level low if ptoc=0 output toggle with ptmanf flag note ptio [1:0] = 10 a?tive high output sele?t he?e ptio [1:0] = 11 toggle output sele?t output not affe?ted ?y ptmanf flag. re?ains high until ?eset ?y pton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ptpol is high ptncclr = 0 ptnm [1:0] = 00 co?pa?e mat?h output mode C ptncclr = 0 (n=0~3) note: 1. w ith ptncclr = 0 C a comparator p match will clear the counter 2. the ptm output pin is controlled only by the ptmanf fag 3. the output pin is reset to initial state by a ptnon bit rising edge
rev. 1.30 94 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 9? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom counte? value 0x3ff ccrp ccra pton ptpau ptpol ccrp int. flag ptmpnf ccra int. flag ptmanf ptm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t output pin set to initial level low if ptoc=0 output toggle with ptmanf flag note ptio [1:0] = 10 a?tive high output sele?t he?e ptio [1:0] = 11 toggle output sele?t output not affe?ted ?y ptmanf flag. re?ains high until ?eset ?y pton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ptpol is high ptmpnf not gene?ated no ptmanf flag gene?ated on ccra ove?flow output does not ?hange ptncclr = 1 ptnm [1:0] = 00 co?pa?e mat?h output mode C ptncclr = 1 (n=0~3) note: 1. w ith ptncclr = 1 C a comparator a match will clear the counter 2. the ptm output pin is controlled only by the ptmanf fag 3. the output pin is reset to initial state by a ptnon rising edge 4. the ptmpnf fag is not generated when ptncclr = 1
rev. 1.30 94 de?e??e? 0?? ?01? rev. 1.30 9 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ti/ct m to s elect this mode, bits p tnm1 and p tnm0 in the p tmnc1 regis ter s hould all be s et to 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the ptm output pin is not used. therefore the above description and t iming diagrams for the compare match out put mod e c an be use d t o un derstand i ts fu nction. as t he pt m ou tput pi n i s no t use d i n this mode, the pin can be used as a normal i/o pin or other pin-shared function. to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively and also the ptnio1 and ptnio0 bits should be set to 10 respectively . the pwm function within the ptm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fe xible. in t he pw m m ode, t he pt ncclr bi t ha s no e ffect a s t he pw m period. b oth o f t he c crp a nd c cra r egisters a re u sed t o g enerate t he pw m wa veform, c crp registers are used to clear the intern al counter and thus control the pwm waveform frequency , while ccra registers are used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the ptnoc bit in the ptmnc1 register is used to select the required polarity of the pwm waveform while the ptnio1 and ptnio0 bits are used to enable the pwm output or to force the ptm output pin to a fxed high or low level. the ptnpol bit is used to reverse the polarity of the pwm output waveform. ? pe ? iod 1~10 ? 3 10 ? 4 duty ccra if f sys = 16mhz, ptm clock source select f sys /4, ccrp = 100b and ccra = 128, the ptm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.30 9 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 97 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom counte? value ccrp ccra ptnon ptnpau ptnpol ccrp int. flag ptmpnf ccra int. flag ptmanf ptm o/p pin (ptnoc=1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if ptnon ?it low counte? reset when ptnon ?etu?ns high pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ptnpol = 1 pwm pe?iod set ?y ccrp ptm o/p pin (ptnoc=0) ptnm [1:0] = 10 pwm output mode (n=0~3) note: 1. here counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when ptnio[1:0] = 00 or 01 4. the ptncclr bit has no infuence on pwm operation
rev. 1.30 9? de?e??e? 0?? ?01? rev. 1.30 97 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom il pls ott m to select this mode, the required bit pairs, ptnm1 and ptnm0 should be set to 10 respectively and also the corresponding ptnio1 and ptnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the ptnon bit, which can be implem ented using the applicatio n program. however in the single pulse mode, the ptnon bit can also be made to automatically change from low to high using the external ptckn_0/ptckn_1 pin, whi ch wi ll i n t urn i nitiate t he si ngle pul se output . w hen t he pt non bit t ransitions t o a high level, the counter will start running and the pulse leading edge will be generated. the ptnon bit should r emain h igh wh en t he p ulse i s i n i ts a ctive st ate. t he g enerated p ulse t railing e dge wi ll b e generated when the ptnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compa re match from comparator a will also automatically clear the ptnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate ptm interrupts. the counter can only be res et back to zero w hen the ptno n bit changes from low to high w hen the counter restarts. in the single pulse mode ccrp is not used. the ptncclr bit is not used. s/w co??and set ptnon o? ptckn_0/ptckn_1 pin t?ansition t?ailing edge s/w co??and clr ptnon o? ccra co?pa?e mat?h ptpn output pin pulse width = ccra value leading edge ptnon ?it 0 1 ptnon ?it 1 0 single pulse gene?ation (n=0~3)
rev. 1.30 98 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 99 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom counte? value ccrp ccra ptnon ptnpau ptnpol ccrp int. flag ptmpnf ccra int. flag ptmanf ptm o/p pin (ptnoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when ptnon ?etu?ns high pulse width set ?y ccra output inve?ts when ptnpol = 1 no ccrp inte??upts gene?ated ptm o/p pin (ptnoc=0) ptckn_0/1 pin softwa?e t?igge? clea?ed ?y ccra ?at?h ptckn_0/1 pin t?igge? auto. set ?y ptckn_0/1 pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? ptnm [1:0] = 10 ptnio [1:0] = 11 single pulse mode (n=0 ~ 3) note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the ptckn_0/1 pin or by setting the ptnon bit high 4. a ptckn_0/1 pin active edge will automatically set the ptnon bit high 5. in the single pulse mode, ptnio [1:0] must be set to 11 and can not be changed.
rev. 1.30 98 de?e??e? 0?? ?01? rev. 1.30 99 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom cat t m to select this mode bits ptnm1 and ptnm0 in the ptmnc0 register should be set to 01 respectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and c an t herefore be use d fo r a pplications suc h a s pu lse wi dth m easurements. t he e xternal si gnal is supplied on the ptpni_0/ ptpni_1 or ptckn_0/ ptckn_1 pin, selected by the ptncapts bit in the ptmnc1 register . the input pin active edge can be either a rising edge, a falling edge or both rising a nd fa lling e dges; t he a ctive e dge t ransition t ype i s se lected usi ng t he pt nio1 a nd pt nio0 bits in the ptmnc1 register . the counter is started when the ptnon bit changes from low to high which is initiated using the application program. when t he re quired e dge t ransition a ppears on t he se lected pt mn i nput pi n t he pre sent va lue i n the counter will be latched into the ccra register and a ptm interrupt generated. irrespective of what events occur on the selected input pin the counter will continue to free run until the ptnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a p tm interrupt w ill als o be generated. counting the number of ov erflow i nterrupt si gnals fro m t he cc rp c an be a use ful m ethod i n m easuring l ong pulse widths. the ptnio1 and ptnio0 bits can select the active trigger edge on the input pin to be a rising edge, falling edge or both edge types. if the ptnio1 and ptnio0 bits are both set high, then no captur e operati on will take place irrespective of what happens on the input pin, however it must be noted that the counter will continue to run. as the ptpni_0/ ptpni_1 or ptckn_0/ ptckn_1 pin is pin shared with other functions, care must be taken if the ptm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the ptncclr, ptnoc and ptnpol bits are not used in this mode.
rev. 1.30 100 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 101 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom counte? value yy ccrp ptnon ptnpau ccrp int. flag ptmpnf ccra int. flag ptmanf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset ptm ?aptu?e input pin xx counte? stop ptnio [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e ptnm [1:0] = 01 captu?e input mode (n=0~3) note: 1. ptnm[1:0] = 01 and active edge set by the ptnio[1:0] bits 2. a ptm capture input pin active edge transfers counter value to ccra 3. the ptncclr bit is not used 4. no output function C ptnoc and ptnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero
rev. 1.30 100 de?e??e? 0?? ?01? rev. 1.30 101 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom aal t diital ct the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. the devices contain an 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. the external or internal analog signal to be converted is determined by the sains and sacs bit felds. additionally note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly configured first. more detailed information about the a/d input signal is described in the a/d converter control registers and a/d converter input signal sections respectively. 8 sains ? ~sains0 ? sacs ? ~sacs0 an0~an7 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. an0 an? an? an7 1?-?it sar adc enadc sadoh[7:0] sadol[7:0] adbz saint sacs[?:0] v bg (1.04v) vref v ri divide? f sys sacks[?:0] av dd savrs[3:0] v r vrefo sains[?:0] sapin vrefo enopa pbs0 opa mux pin-sha?ed sele?tion av dd v r a/d conve?te? st?u?tu?e
rev. 1.30 10 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 103 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom a/d ct rist dsiti overall operation of the a /d converter is controlled us ing f ve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. sadol(adrfs=0) d3 d ? d1 d0 sadol(adrfs=1) d7 d ? d ? d4 d3 d ? d1 d0 sadoh(adrfs=0) d11 d10 d9 d8 d7 d ? d ? d4 sadoh(adrfs=1) d11 d10 d9 d8 sadc0 start adbz enadc adrfs sacs ? sacs1 sacs0 sadc1 sains ? sains1 sains0 sacks ? sacks1 sacks0 sadc ? enopa vbgen savrs3 savrs ? savrs1 savrs0 a/d conve?te? registe? list a/d conve?te? data registe?s C sadol? sadoh as the devices contain an internal 12-bit a/d converter , it requires two data registers to store the converted value. these are a high byte register , known as sadoh, and a low byte register , known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is ut ilised, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he adrfs bi t i n t he sadc0 register as shown in the accompanying table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. note that the a/d converter data register contents will not be cleared to zero if the a/d converter is disabled. 0 d11 d10 d9 d8 d7 d ? d ? d4 d3 d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d ? d ? d4 d3 d ? d1 d0 a/d data registe?s a/d conve?te? cont?ol registe?s C sadc0? sadc1? sadc? to control the function and operation of the a/d converter , several control registers known as sadc0, sadc1 and sadc2 are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter , the digitised data format, t he a/ d c lock so urce a s we ll a s c ontrolling t he st art f unction a nd m onitoring t he a/ d converter busy status. the sacs2~sacs0 bits in the sadc0 register are used to determine which external channel input is selected to be converted. the sains2~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. if the sains2~sains0 bits are set to 000, the external analog channel input is selected to be converted and the sacs2~sacs0 bits can determine which external channel is selected to be converted. if the sains2~sains0 bits are set to 001~01 1, the a v dd voltage is selected to be converted. if the sains2~sains0 bits are set to 101~1 11, the op a output voltage is selected to be converted. when v ref or v bg is selected as adc input or adc reference voltage, the opa needs to be enabled by setting enopa to 1frst.
rev. 1.30 10? de?e??e? 0?? ?01? rev. 1.30 103 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom note that when the programs select external signal and internal signal as an adc input signal simultaneously, then the hardware will only choose the internal signal as an adc input. in addition, if the programs select external reference voltage v ref and the internal reference voltage v bg as adc reference voltage, then the hardware will only choose the internal reference voltage v bg as an adc reference voltage input. care must be take n when the intern al analog signal is selected to be converted. if the internal analog signal is selected to be converted, the selected external input pin determ ined by the sacs2~sacs0 bits must never be configured as a/d input function by properly setting the relevant pin-shared control bi ts. ot herwise, t he e xternal c hannel i nput wi ll be c onnected t ogether wi th t he i nternal analog signal. this will result in unpredictable situations such as an irreversible damage. the pin-shared function control registers, named p as0, p as1 and pbs0, contain the corresponding pin-shared selectio n bits which dete rmine which pins on port a and port b are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in additio n, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. na ? e start adbz enadc adrfs sacs ? sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start a/d conversion 01: reset the a/d converter and set adbz to 0 10: start a/d conversion and set adbz to 1 bit 6 adbz : adc busy fag 0: a/d conversion ended or no conversion 1: a/d is busy bit 5 enadc : adc enable/disable control register 0: disable 1: enable bit 4 adrfs : a/d output data format selection bit 0: adc output data format sadoh=d[11:4]; sadol=d[3:0] 1: adc output data format sadoh=d[11:8]; sadol=d[7:0] bit 3~2 unimplemented, read as "0" bit 1~0 sacs2~sacs0 : adc input channels selection 000: adc input channel comes from an0 001: adc input channel comes from an1 010: adc input channel comes from an2 011: adc input channel comes from an3 100: adc input channel comes from an4 101: adc input channel comes from an5 110: adc input channel comes from an6 111: adc input channel comes from an7
rev. 1.30 104 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 10? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom adc rist it 6 4 2 0 na ? e sains ? sains1 sains0 sacks ? sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~5 sains2~sains0 : internal adc input channel selection bit 000: adc input only comes from external pin 001: adc input also comes from a v 010: adc input also comes from a v /2 011: adc input also comes from a v /4 101: adc input also comes from v r 110: adc input also comes from v r /2 111: adc input also comes from v r /4 other v alues: same as 000 note: v r is op a output voltage. v r can be one of v ref / v ref 2 / v ref 3 / v ref 4 / v bg 2 / v bg 3 / v bg 4. bit 4~3 unimplemented, read as 0 bit 2~0 sacks2~sacks0 : adc clock rate selection bit 000: f 001: f / 2 010: f / 4 011: f / 8 100: f / 16 101: f / 32 110: f / 64 111: f /128 na ? e enopa vbgen savrs3 savrs ? savrs1 savrs0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 enopa : opa enable/disable control register 0: disable 1: enable bit 6 vbgen : bandgap buffer disable/enable control bit 0: disable 1: enable bit 5~4 unimplemented, read as 0 bit 3~0 savrs3~savrs0 : adc reference voltage selection bit 0000: adc reference voltage comes from a v 0001: adc reference voltage comes from v ref 0010: adc reference voltage comes from v ref 2 0011: adc reference voltage comes from v ref 3 0100: adc reference voltage comes from v ref 4 1001: inhibit to use 1010: adc reference voltage comes from v bg 2 1011: adc reference voltage comes from v bg 3 1100: adc reference voltage comes from v bg 4 other v alues: same as 0000
rev. 1.30 104 de?e??e? 0?? ?01? rev. 1.30 10 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom note: 1. when selecting v ref , v ref 2, v ref 3 or v ref 4 as the adc reference voltage, the pin shared control register should be correctly set to select vref as the input. 2. v bg =1.04v 3. when savrs3=1, then opa selects v bg as input. 4. if the program select s an external reference voltage v ref and the internal reference voltage v bg as the adc reference voltage, then the hardware will only choose the internal reference voltage v bg as an adc reference voltage input. the st art bit is used to start and reset the a/d converter . when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the st art bit is brought from low to high but not low again, the adbz bit in the sadc0 register will be cleared to zero and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the adbz bi t i n t he sadc0 re gister i s use d t o i ndicate whe ther t he a nalog t o di gital c onversion process is in process or not. when the a/d converter is reset by setting the st art bit from low to high, the adbz fag will be cleared to 0. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleare d to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program fow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. although the a/d clock source is determined by the system clock f sys , and by bits sack2~sack0, there a re so me l imitations o n t he m aximum a/ d c lock so urce sp eed t hat c an b e se lected. as t he recommended va lue of pe rmissible a/ d c lock pe riod, t adck , i s from 0.5 s t o 10s, c are m ust be taken for system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the sack2~sack0 bits should not be set to 000b or 1 1xb. doing so will give a/d clock periods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d c lock period which may result in inaccurate a/d conversion values. controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he enadc bit in the sadc0 register . this bit must be set high to power on the a/d converter . when the e nadc b it i s se t h igh t o p ower o n t he a/ d c onverter i nternal c ircuitry a c ertain d elay, a s indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by confguring the corresponding pin-shared control bits, if the enadc bit is high then some power will still be consumed. in power conscious applications it is therefore recom mended that the enadc is set low to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the internal adc power o r f rom a n e xternal r eference so urces su pplied o n p in vr ef o r v bg v oltage. t he d esired selection i s m ade usi ng t he sa vrs3~ sa vrs0 bi ts. as t he vre f pi n i s pi n-shared wi th ot her functions, when the vref pin is selected as the reference voltage supply pin, the vref pin-shared function control bits should be properly confgured to disable other pin functions. when v ref o r v bg i s se lected by adc i nput or adc re ference vol tage, t he op a ne eds t o be e nabled by se tting enopa=1.
rev. 1.30 10 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 107 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom r lta ar0 dsiti av dd 0000 adc ? efe ? en ? e voltage ? o ? es f ? o ? av dd v ref 0001 adc ? efe ? en ? e voltage ? o ? es f ? o ? exte ? nal v ref v ref ? 0010 adc ? efe ? en ? e voltage ? o ? es f ? o ? exte ? nal v ref ? v ref 3 0011 adc ? efe ? en ? e voltage ? o ? es f ? o ? exte ? nal v ref 3 v ref 4 0100 adc ? efe ? en ? e voltage ? o ? es f ? o ? exte ? nal v ref 4 v bg ? 1010 adc ? efe ? en ? e voltage ? o ? es f ? o ? v bg ? v bg 3 1011 adc ? efe ? en ? e voltage ? o ? es f ? o ? v bg 3 v bg 4 1100 adc ? efe ? en ? e voltage ? o ? es f ? o ? v bg 4 a/d conve?te? refe?en?e voltage sele?tion a/d conve?te? input signal all of the a/d analog input pins are pin-shared with the i/o pins on port a and port b as well as other functions. the corredponding selection bits for each i/o pin in the p as0, p as1 and pbs0 registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the pin-shared function control bits confgure its corresponding pin as an a/ d a nalog c hannel i nput, t he p in wi ll b e se tup t o be a n a/ d c onverter e xternal c hannel i nput and the original pin functions disabled. in this way , pins can be changed under program control to change t heir func tion be tween a/ d i nputs a nd ot her func tions. al l pul l-high re sistors, whi ch a re setup through register programming, will be automatically disconnecte d if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p ac and pbc port control register to enable the a/d input as when the pin-shared function control bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the sa vrs[3:0] in the sadc2 register . the selected a/d reference voltage can be output on the vrefo pin. the analog input values must not be allowed to exceed the value of v ref. a com plete a/d conversi on contains two parts, dat a sampli ng and dat a conversi on. the dat a sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. t herefore a total of 16 a/ d clock cycles for an a/ d conversion which is defned as t adc are necessary. maximum single a/d conversion rate = a/d clock period / 16 however, there is a usage limitation on the next a/d conversion after the current conversion is complete. when the current a /d convers ion is complete, the converted digital data w ill be s tored in the a/d data register pair and then latched after half an a/d clock cycle. if the st art bit is set to 1 i n h alf a n a/ d c lock c ycle a fter t he e nd o f a/ d c onversion, t he c onverted d igital d ata st ored in the a/d data register pair will be changed. therefore, it is recommended to initiate the next a/d conversion after a certain period greater than half an a/d clock cycle at the end of current a/d conversion.
rev. 1.30 10? de?e??e? 0?? ?01? rev. 1.30 107 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom
? ? ? ? ? ?? ? ? ? ? - ?? - ? ? ? ? ? a/d conversion timing summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion frequency by sacks2~ sacks0 ? step 2 enable the adc by set enadc=1 ? step 3 select which pins will be confgure as adc analog inputs by setting the pin-shared register. ? step 4 if input comes from external channel, set sains[2:0]=000 and then set sacs bit fields to corresponding input channel if input comes from internal input, set sains[2:0] to corresponding internal input source ? step 5 select reference voltage comes from external v ref , av dd or v bg by savrs[3:0] note: if select v ref as reference voltage, set pbs0[1:0] = 1, 0 ? step 6 select adc output data format by adrfs ? step 7 if adc interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bits, ade, must both set high in advance. ? step 8 the a/d convert procedure can now be initialized by set st art from low to high and then low again ? step 9 if adc is under conversion, adbz=1. after a/d conversion process is completed, the adbz fag will go low , and then output data can be read from sadoh and sadol registers. if the adc i nterrupt i s enabl ed and the st ack i s not ful l, dat a can be ac quired by int errupt servic e program. another way to get the a/d output data is polling the adbz fag.
rev. 1.30 108 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 109 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pai csiatis during m icrocontroller ope rations where t he a/d c onverter i s not be ing use d, t he a/d i nternal circuitry c an b e swi tched o ff t o r educe p ower c onsumption, b y c learing t he e nadc b it i n t he sadc0 regist er. when thi s happens, the int ernal a/ d converter ci rcuits wi ll not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. as the devices contain a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= (av dd or v ref ) / 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (av dd or v ref ) / 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.

? ? ? ? ? ? ?? ? ?
? ideal a/d transfer function
rev. 1.30 108 de?e??e? 0?? ?01? rev. 1.30 109 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom a/d pai eals the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. clr a de ; disable adc interrupt mov a,0bh mov sadc1,a ; s elect f sys /8 as a/d clock and switch off the bandgap reference ; voltage set enadc mov a,03h ; s etup p bs0 r egister t o c onfgure p in a n0 mov pbs0,a mov a,20h mov sadc0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : start_conversion: clr start ; h igh p ulse o n s tart b it t o i nitiate c onversion set start ; r eset a /d clr start ; s tart a /d polling_eoc: sz adbz ; p oll t he s adc0 r egister a dbz b it t o d etect e nd o f a /d c onversion jmp polling_eoc ; c ontinue p olling mov a,sadol ; re ad l ow b yte c onversion re sult v alue mov sadol_buffer,a ; s ave r esult t o us er d efned r egister mov a,sadoh ; re ad h igh b yte c onversion re sult v alue mov sadoh_buffer,a ; s ave r esult t o us er d efned r egister : : jmp start_conversion ; st art n ext a/d c onversion
rev. 1.30 110 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 111 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom eal si th itt th t tt th si clr a de ; disable adc interrupt mov a,0bh mov sadc1,a ; s elect f sys /8 as a/d clock and switch off the bandgap reference ; voltage set enadc mov a,03h ; s etup p bs0 r egister t o c onfgure p in a n0 mov pbs0,a mov a,20h mov sadc0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter start_conversion: clr start ; h igh p ulse o n st art b it t o i nitiate c onversion set start ; r eset a /d clr start ; s tart a /d clr adf ; c lear a dc i nterrupt re quest f ag set a de ; enable adc interrupt set emi ; e nable gl obal i nterrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; s ave a cc t o u ser d efned m emory mov a,status mov status_stack,a ; s ave st atus t o us er d efned m emory : : mov a,sadol ; re ad l ow b yte c onversion re sult v alue mov sadol_buffer,a ; s ave r esult t o us er d efned r egister mov a,sadoh ; re ad h igh b yte c onversion re sult v alue mov sadoh_buffer,a ; s ave r esult t o us er d efned r egister : : exit_int_isr: mov a,status_stack mov status,a ; restore s tatus f rom u ser d efned m emory mov a,acc_stack ; r estore a cc fr om u ser d efned m emory reti
rev. 1.30 110 de?e??e? 0?? ?01? rev. 1.30 111 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ial ta ml m these devices contain a serial interface module, which includes both the four -line spi interface or two-line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. ha ving re latively si mple c ommunication prot ocols, t hese se rial i nterface t ypes a llow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory , etc. the sim interface pins are pin-shared with other i/o pins and therefore the sim i nterface func tional pi ns m ust fi rst be se lected usi ng t he c orresponding pi n-shared func tion selection bits. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 registe r. these pull-high resistors of the sim pin-shared i/o pins are selected using pull- high control registers when the sim function is enabled and the corresponding pins are used as sim input pins. the spi interface is often used to communicate with external peripheral devices such as sensors, flash or e eprom m emory de vices, e tc. ori ginally de veloped by mot orola, t he four l ine spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the devices can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a single master , these devices provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi master/slave connection spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface pins must frst be selected by confguring the pin-shared function selection bits and setting the correct bits in the simc0 and simc2 registers. after the desired spi confguration has been set it can be disabled or enabled us ing the s imen bit in the s imc0 regis ter. communication betw een devices connected to t he spi i nterface i s c arried out i n a sl ave/master m ode wi th a ll da ta t ransfer i nitiations be ing implemented by the master . the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to 1 to enable scs pin function, clear csen bit to 0 the scs pin will be foating state. the spi function in this device offers the following features:
rev. 1.30 11 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 113 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen.

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? ? ? ? - ? ?? ? ??? ? ? ? spi block diagram spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. simc0 sim ? sim1 sim0 simdeb1 simdeb0 simen simicf simc ? d7 d ? ckpolb ckeg mls csen wcol trf simd d7 d ? d ? d4 d3 d ? d1 d0 spi registe?s list ? the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown
rev. 1.30 11 ? de?e??e? 0?? ?01? rev. 1.30 113 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmi ssion clock frequency . register simc2 is used for other control functions such as lsb/msb selection, write collision fag, etc. ? na ? e sim ? sim1 sim0 simdeb1 simdeb0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is ctm1 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operatin g mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e selection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from ctm1. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as 0 bit 3~2 simdeb1~simdeb0 : i 2 c debounce t ime selection described elsewhere. bit 1 simen : sim enable control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minim um value. when the bit is high the sim interface is enabled. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be frst i nitialised by t he a pplication progra m whi le t he re levant i 2 c fags suc h a s hcf , haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim spi slave mode incomplete t ransfer flag 0: sim spi slave mode incomplete condition not occurred 1: sim spi slave mode incomplete condition occured this bit is only available when the sim is confgured to operate in an spi slave mode. if the spi operate s in the slave mode with the simen and csen bits both being set to 1 but the scs line is pulled high by the external master device before the spi data transfer is completely fnished, the simicf bit will be set to 1 togethe r with the trf bit. when this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. however , the trf bit will not be set to 1 if the simicf bit is set to 1 by software application program.
rev. 1.30 114 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 11 ? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? na ? e d7 d ? ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bits these bits can be read or written by the application program. bit 5 ckpolb : spi clock line base condition selection 0: the sck line will be high when the clock is inactive. 1: the sck line will be low when the clock is inactive. the ckpolb bi t de termines the ba se condition of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 ckeg : spi sck clock active edge type selection ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inact ive. when the ckpolb bit is low , then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb frst 1: msb frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low , then the scs pin will be disabled and placed into i/o pin or other pin-shared functions. if the bit is high, the scs pin will be enabled and used as a select pin. bit 1 wcol : spi write collision fag 0: no collision 1: collision the wcol fag is used to detect whether a data collision has occurred or not. if this bit is high, it means that data has been attempted to be written to the simd register duting a data transfer operation. this writing operation will be ignored if data is being transferred. this bit can be cleared by the application program. bit 0 trf : spi t ransmit/receive complete fag 0: spi data is being transferred 1: spi data transfer is completed the trf bit is the t ransmit/receive complete fag and is set to 1 automatically when an spi data transfer is completed, but must cleared to 0 by the application program. it can be used to generate an interrupt.
rev. 1.30 114 de?e??e? 0?? ?01? rev. 1.30 11 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom p ciati after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register , transmission/reception will begin simultaneously . when the data t ransfer i s c omplete, t he t rf fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register . the master should output a scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
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? ? spi master mode timing

? ? ? ? ??? ? - ? ? ?? spi slave mode timing ? ckeg=0
rev. 1.30 11 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 117 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom

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rev. 1.30 11 ? de?e??e? 0?? ?01? rev. 1.30 117 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 2 c ta the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom m emory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, it is the master device that has overall control of the bus. for these devices, which only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode.

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? ?? ? i 2 c block diagram
rev. 1.30 118 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 119 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom
the simdeb1 and simdeb0 bits determine the debounce time of the i 2 c interface. this uses the system clock to in ef fect add a debounce time to the external clock to reduce the possibility of gl itches on t he c lock l ine c ausing e rroneous ope ration. t he de bounce t ime, i f se lected, c an be chosen to be either 2 or 4 sys tem clocks. t o achieve the required i 2 c data trans fer speed, there exists a relationship between the system clock, f , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no devoun ? e f sys > ? mhz f sys > ? mhz ? syste ? ? lo ? k de ? oun ? e f sys > 4 mhz f sys > 10 mhz 4 syste ? ? lo ? k de ? oun ? e f sys > 8 mhz f sys > ? 0 mhz i 2 c minimum f sys frequency i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima, and one data register , simd. the simd register , which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. note that the sima register also has the name simc2 which is used by the spi function. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 simdeb1 simdeb0 simen simicf simc1 hcf haas hbb htx txak srw iamwu rxak sima a ? a ? a4 a3 a ? a1 a0 simd d7 d ? d ? d4 d3 d ? d1 d0 simtoc simtoen simtof simtos ? simtos4 simtos3 simtos ? simtos1 simtos0 i 2 c registers list
rev. 1.30 118 de?e??e? 0?? ?01? rev. 1.30 119 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? the simd register is used to store the data being transmitted and received. the same register is used by bot h t he spi a nd i 2 c fun ctions. be fore t he de vice wri tes da ta t o t he i 2 c bus, t he a ctual da ta t o be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the device can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown ? the sima registe r is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. na ? e a ? a ? a4 a3 a ? a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown bit 7~1 a6~a0 : i 2 c slave address a6~a0 is the i 2 c slave address bit 6 ~ bit 0 bit 0 undefned bit the bit can be read or written by the application program. there are also two control registers for the i 2 c interface, simc0 and simc1. the register simc0 is use d t o c ontrol t he e nable/disable func tion a nd t o se t t he da ta t ransmission c lock fre quency.the simc1 register contains the relevant fags which are used to indicate the i 2 c communication status.
rev. 1.30 1 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?1 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? na ? e sim ? sim1 sim0 simdeb1 simdeb0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is ctm1 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operatin g mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e selection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from ctm1. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as 0 bit 3~2 simdeb1~simdeb0 : i 2 c debounce t ime selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen : sim enable control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minim um value. when the bit is high the sim interface is enabled. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be frst i nitialised by t he a pplication progra m whi le t he re levant i 2 c fags suc h a s hcf , haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim spi slave mode incomplete t ransfer flag described elsewhere.
rev. 1.30 1?0 de?e??e? 0?? ?01? rev. 1.30 1 ? 1 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? na ? e hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r/w r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus data transfer completion fag 0: not address match 1: address match the haas fa g i s t he a ddress m atch fa g. t his fa g i s use d t o de termine i f t he sl ave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx : i 2 c slave device transmitter/receiver selection 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave does not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9 th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i 2 c address match w ake-up control 0: disable 1: enable C must be cleared by the application program after wake-up this bit should be set to 1 to enabl e the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation.
rev. 1.30 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?3 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom bit 0 : i 2 c bus receive acknowledge fag 0: slave receives acknowledge fag 1: slave does not receive acknowledge fag the r xak fl ag i s t he r eceiver a cknowledge f lag. w hen t he r xak f lag i s 0, i t means that a acknowledge signal has been received at the 9 th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. t he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas and simt of bits to determine whether t he i nterrupt sou rce o riginates fr om a n a ddress m atch, 8 -bit d ata t ransfer c ompletion o r 2 c bus time-out occurrence. during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8 th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 select the sda and scl pin function by pin-shared registers ? step 2 set the sim2~sim 0 bits to 1 10 and simen bit to 1 in the simc0 register to enable the i 2 c bus. ? step 3 write the slave address of the device to the i 2 c bus address register sima. ? step 4 set the sim interrupt enable bit sime of the interrupt control register to enable the sim interrupt.
rev. 1.30 1?? de?e??e? 0?? ?01? rev. 1.30 1 ? 3 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom

? ? ? ? ?? -? ? ? ? ?? ? ? ? ? ?? i 2 c bus start signal the st art signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8 th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9 th bit. the slave device will also set the status fag haas when the addresses match. as a n i 2 c bus i nterrupt c an c ome fro m t hree sourc es, whe n t he progra m e nters t he i nterrupt subroutine, the haas and simt of bits should be examined to see whether the interrupt source has come from a matching slave address, the completion of a data byte transfer or the i 2 c bus time-out occurrence. when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line. the sr w bit in the simc1 registe r defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver.
rev. 1.30 1 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 2 c s la ass awl ial after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1. if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0. the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. t he o rder o f se rial b it t ransmission i s t he msb fr st a nd t he l sb l ast. after receipt of 8-bits of data, the receiver must transmit an acknowle dge signal, level 0, before it can receive the next data byte. if the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register . if setup as a receive r, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9 th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
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- ? ? note: *when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.30 1?4 de?e??e? 0?? ?01? rev. 1.30 1 ?? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom
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?? ? ?? i 2 c bus isr flow chart i 2 c time-out control in order to reduce the i 2 c lockup problem due to reception of erroneous clock sources , a time-out function is provided. if the clock source connected to the i 2 c bus is not received for a while, then the i 2 c circu itry and registers will be reset after a certain time-out period. the time-out counter starts to count on an i 2 c bus st art & address match condition, and is cle ared by an scl falling edge. before the next s cl falling edge arrives , if the time elaps ed is greater than the time-out period specifed by the simt oc register , then a time-out condition will occur . the time-out function will stop when an i 2 c stop condition occurs.
rev. 1.30 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?7 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom

i 2 c time-out when an i 2 c time-out counter overfow occurs, the counter will stop and the simt oen bit will be c leared t o z ero a nd t he simt of bi t wi ll be se t hi gh t o i ndicate t hat a t ime-out c ondition ha s occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrrupt vector . when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: simd ? sima ? simc0 no ? hange simc1 reset to por ? ondition i ? c registe? afte? ti?e-out the simtof fag can be cleared by the application program. there are 64 time-out period selections which can be selected using the simt os bits in the simt oc register . the time-out duration is calculated by the formula: ((1~64) (32/f sub )). this gives a time-out period which ranges from about 1ms to 64ms. ? na ? e simtoen simtof simtos ? simtos4 simtos3 simtos ? simtos1 simtos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : sim i 2 c t ime-out control 0: disable 1: enable bit 6 : sim i 2 c t ime-out fag 0: no time-out occurred 1: t ime-out occurred bit 5~0 : sim i 2 c t ime-out period selection i 2 c t ime-out clock source is f sub /32 i 2 c t ime-out period is equal to (simtos [5:0] + 1) f sub 32
rev. 1.30 1?? de?e??e? 0?? ?01? rev. 1.30 1 ? 7 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom uart ta the ht66f0082 device contains an integrated full-duplex asynchronous serial communications uart i nterface that ena bles c ommunication wi th ext ernal devi ces t hat cont ain a se rial i nterface. the uar t function has many features and can transmit and receive data serially by transferring a f rame o f d ata wi th e ight o r n ine d ata b its p er t ransmission a s we ll a s b eing a ble t o d etect e rrors when the data is overwritten or incorrectly framed. the uar t functio n possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. the integrated uart function contains the following features: ? full-duplex, universal asynchronous receiver and t ransmitter (uart) communication ? 8 or 9 bits character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect (last character bit=1) ? transmitter and receiver enabled independently ? 2-byte deep fifo receive data buffer ? transmit and receive interrupts ? interrupts can be initialized by the following conditions: ? transmitter empty ? transmitter idle ? receiver full ? receiver overrun ? address mode detect ? rx pin wake-up interrupt (rx enable, rx falling edge) msb lsb t?ans?itte? shift registe? (tsr) msb lsb re?eive? shift registe? (rsr) tx pin rx pin baud rate gene?ato? tx registe? (txr) rx registe? (rxr) data to ?e t?ans?itted data ?e?eived buffe? f sys mcu data bus uart data t?ansfe? blo?k diag?a?
rev. 1.30 1 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?9 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom uart etal pi ta to communicate with an external serial interface, the internal uar t has two external pins known as tx and rx. the tx and rx pins are the uar t transmitter and receiver pins respectively . the tx and rx pin function should frst be selected by the corresponding pin-shared function selection register before the uar t function is used. along with the uar ten bit, the txen and rxen bits, if set, will automatically setup these i/o or other pin-shared functional pins to their respective tx output a nd rx i nput c onditions a nd di sable a ny pu ll-high re sistor op tion whi ch m ay e xist on t he tx and rx pins. when the tx or rx pin function is disabled by clearing the uar ten, txen or rxen b it, t he t x o r r x p in wi ll b e se t t o a fo ating st ate. at t his t ime wh ether t he i nternal p ull- high resistor is connected to the tx or rx pin or not is determined by the corresponding i/o pull- high function control bit. the above block diagram shows the overall data transfer structure arrangement for the uar t interface. the actual data to be transmitted from the mcu is frst transferred to the txr register by the application program. the data will then be transferred to the t ransmit shift register from where it wi ll be shi fted out , l sb frst , ont o t he t x pi n a t a ra te c ontrolled by t he ba ud ra te ge nerator. only t he t xr r egister i s m apped o nto t he mc u da ta me mory, t he t ransmit sh ift r egister i s n ot mapped and is therefore inaccessible to the application program. data to be received by the uar t is accepted on the external rx pin, from where it is shifted in, lsb fi rst, t o t he re ceiver shi ft re gister a t a ra te c ontrolled by t he ba ud ra te ge nerator. w hen the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buf fered and can be manipulated by the application program. only the rxr register i s m apped ont o t he mcu dat a me mory, t he re ceiver shi ft re gister i s not m apped a nd i s therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register in the data memory . this shared register known as the txr_rxr register is used for both data transmission and data reception. there are fve control registers associated with the uar t function. the usr, ucr1 and ucr2 registers c ontrol t he o verall f unction o f t he uar t, wh ile t he b rg r egister c ontrols t he b aud r ate. the actua l data to be transmitted and received on the serial interface is managed through the txr_ rxr data register. usr perr nf ferr oerr ridle rxif tidle txif ucr1 uarten bno pren prt stops txbrk rx8 tx8 ucr ? txen rxen brgh adden wake rie tiie teie txr_ rxr d7 d ? d ? d4 d3 d ? d1 d0 brg d7 d ? d ? d4 d3 d ? d1 d0 uart registe? list
rev. 1.30 1?8 de?e??e? 0?? ?01? rev. 1.30 1 ? 9 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ur ist the usr register is the status register for the uart, which can be read by the program to determine the present status of the uar t. all fags within the usr register are read only . further explanation on each of the fags is given below. na ? e perr nf ferr oerr ridle rxif tidle txif r/w r r r r r r r r por 0 0 0 0 1 0 1 1 bit 7 perr : parity error fag 0: no parity error is detected 1: parity error is detected the perr fag is the parity error fag. when this read only fag is 0, it indicates a parity error has not been detected. when the fag is 1, it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise fag 0: no noise is detected 1: noise is detected the nf fag is the noise fag. when this read only fag is 0, it indicates no noise condition. when the fag is 1, it indicates that the uar t has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of as overrun. the n f fag can be cleared by a softw are sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 5 ferr : framing error fag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is 0, it indicates that t here i s n o f raming e rror. w hen t he fa g i s 1, i t i ndicates t hat a f raming e rror has been detected for the current character . the fag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 4 oerr : overrun error fag 0: no overrun error is detected 1: overrun error is detected the oerr fag is the overrun error fag which indicates when the rece iver buf fer has overfowed. when this read only fag is 0, it indicates that there is no overrun error . when the fag is 1, it indicates that an overrun error occurs which will inhibit further transfers to the rxr receive data register . the fag is cleared by a software sequence, which is a read to the s tatus regis ter u sr follow ed by an acces s to the rx r data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is 0, it indicates that the receiver is between the init ial detection of the start bit and the completion of the s top bit. when the f ag is 1, it indicates that the receiver is idle. betw een the completion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart receiver is idle and the rx pin stays in logic high condition.
rev. 1.30 130 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 131 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom bit 2 : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif fag is the receive data register status fag. when this read only fag is 0, it indicates that the rxr read data register is empty . when the fag is 1, it indicates that t he r xr r ead d ata r egister c ontains n ew d ata. w hen t he c ontents o f t he sh ift register are trans ferred to the rx r regis ter, an interrupt is generated if rie=1 in the ucr2 register . if one or more errors are detected in the received word, the appropriate receive-related fags nf , ferr, and/or perr are set within the same clock cycle. the rxif fag is clear ed when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 : t ransmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle flag is known as the transmission complete flag. when this read only fag i s 0, i t i ndicates t hat a t ransmission i s i n p rogress. t his fa g wi ll b e se t t o 1 when the txif fag is 1 and when there is no transmit data or break character being transmitted. when tidle is equal to 1, the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared by reading the usr register with tidle set and then writing to the txr register . the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 : t ransmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is 0, it indicat es that the character is not transferred to the transmitter shift register . when the fag is 1, it indicates that the transmitter shift register has received a character from the txr data register . the txif flag is cleared by reading the uar t status register (usr) with txif set and then writing to the txr data register . note that when t he t xen b it i s se t, t he t xif fa g b it wi ll a lso b e se t si nce t he t ransmit d ata register is not yet full. ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uar t function, such as overall on/of f control, parity control, data transfer bit length etc. further explanation on each of the bits is given below. bit 7 6 5 4 3 2 1 0 na ? e uarten bno pren prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 0 0 x 0 x unknown bit 7 : uart function enable control 0: disable uart. tx and rx pins are in a foating state 1: enable uart. tx and rx pins function as uart pins the uarten bit is the uart enable bit. w hen this bit is equal to 0, the uart will be disabled and the rx pin as well as the tx pin will be in a foating state. when the bit is equal to 1, the uar t will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits. when the uar t is disabled, it will empty the buf fer so any character remaining in the buf fer will be discarded. in addition, the value of the baud rate counter will be reset. if the uar t is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif , oerr, ferr, perr and nf bits will be cle ared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaf fected. if the uar t is active and the uar ten bit is
rev. 1.30 130 de?e??e? 0?? ?01? rev. 1.30 131 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom cleared, all pending transmis sions and receptions will be terminated and the module will be reset as defined above. when the uar t is re-enabled, it will restart in the same confguration. bit 6 : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to 1, a 9-bit data length format will be selected. if the bit is equal to 0, then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively. note: 1. if bno=1 (9-bit data transfer), parity function is enabled, the 9th bit of data is the parity bit which will not be transferred to rx8. 2. if bno=0 (8-bit data transfer), parity function is enabled, the 8th bit of data is the parity bit which will not be transferred to rx7. bit 5 : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to 1, the parity function will be enabled. if the bit is equal to 0, then the parity function will be disabled. bit 4 : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to 1, odd parity type will be selected. if the bit is equal to 0, then even parity type will be selected. bit 3 : number of stop bits selection 0: one stop bit format is used 1: t wo stop bits format is used this bit determine s if one or two stop bits are to be used for the tx pin. when this bit is equal to 1, two stop bits are used. if this bit is equal to 0, then only one stop bit is used. bit 2 : t ransmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the t ransmit break character bit. when this bit is 0, there are no break characte rs and the tx pin operates normally . when the bit is 1, there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to 1, after the buf fered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. bit 0 : t ransmit data bit 8 for 9-bit data transfer format (write only) this bit is only us ed if 9-bit data transfers are us ed, in w hich cas e this bit location will st ore t he 9 th b it o f t he t ransmitted d ata k nown a s t x8. t he b no b it i s u sed t o determine whether data transfers are in 8-bit or 9-bit format.
rev. 1.30 13 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 133 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ucr2 ist the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functio ns is to control the basic enable/disable operation of the uar t t ransmitter and receiver as well as enabling the various uar t interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below. na ? e txen rxen brgh adden wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 txen : uart t ransmitter enabled control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txen is the t ransmitter enable bit. when this bit is equal to 0, the transmitter will be disabled with any pending data transmissions being aborted. in addition the buf fers will be reset. in this situation the tx pin will be set in a foating state. if the txen bit is equal to 1 and the uar ten bit is also equal to 1, the transmitter will be enabled and the tx pin will be controlled by the uar t. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter . if this situation occurs, the tx pin will be set in a foating state. bit 6 rxen : uart receiver enabled control 0: uart receiver is disabled 1: uart receiver is enabled the bit named rxen is the receiver enable bi t. when this bit is equal to 0, the receiver will be disabled with any pending data receptions being aborted. in addition the receive buf fers will be reset. in this situation the rx pin will be set in a foating state. i f t he r xen b it i s e qual t o 1 a nd t he uar ten b it i s a lso e qual t o 1, t he receiver will be enabled and the rx pin will be controlled by the uar t. clearing the rxen bit during a reception will cause the data reception to be aborted and will reset the receiver. if this situation occurs, the rx pin will be set in a foating state. bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator . this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uar t. if this bit is equal to 1, the high speed mode is selected. if the bit is equal to 0, the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detection function is disabled 1: address detection function is enabled the bi t na med adde n i s t he a ddress de tect fu nction e nable c ontrol bi t. w hen t his bit is equal to 1, the address detect function is enabled. when it occurs, if the 8th bit, which corresponds to rx7 if bno=0 or the 9th bit, which corresponds to rx8 if bno=1, ha s a va lue of 1, t hen t he re ceived word wi ll be i dentifed a s a n a ddress, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit d epending o n t he v alue o f b no. i f t he a ddress b it k nown a s t he 8 th o r 9 th b it o f t he received word is 0 with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded.
rev. 1.30 13? de?e??e? 0?? ?01? rev. 1.30 133 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom bit 3 : rx pin falling edge wake-up function enable control 0: rx pin wake-up function is disabled 1: rx pin wake-up function is enabled this bi t e nables or di sables t he re ceiver wa ke-up func tion. if t his bi t i s e qual t o 1 and the device is in the idle0 or sleep mode, a falling edge on the rx input pin will wake-up the device. if this bit is equal to 0 and the device is in the idle or sleep mode, any edge transitions on the rx pin will not wake-up the device. bit 2 : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the rece iver interrupt. if this bit is equal to 1 and when the receiver overrun fag oerr or receive data available fag rxif is set, the uar t interrupt request fag will be set. if this bit is equal to 0, the uar t interrupt request fag will not be infuenced by the condition of the oerr or rxif fags. bit 1 : t ransmitter idle interrupt enable control 0: t ransmitter idle interrupt is disabled 1: t ransmitter idle interrupt is enabled this bit enables or disables the transmitter idle interrupt. if this bit is equal to 1 and when t he t ransmitter i dle fa g t idle i s se t, due t o a t ransmitter i dle c ondition, t he uart interrupt request fag will be set. if this bit is equal to 0, the uar t interrupt request fag will not be infuenced by the condition of the tidle fag. bit 0 : t ransmitter empty interrupt enable control 0: t ransmitter empty interrupt is disabled 1: t ransmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 and when the transmitter empty fag txif is set, due to a transmitter empty condition, the uar t interrupt re quest fl ag will be set. if this bi t is equal to 0 , the uar t interrupt request fag will not be infuenced by the condition of the txif fag. txr_rxr register the txr_rxr register is the data register which is used to store the data to be transmitted on the tx pin or being received from the rx pin. bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 : uart t ransmit/receive data bit 7 ~ bit 0
rev. 1.30 134 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 13? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom a rat at to setup the speed of the serial data communication, the uar t function contains its own dedicated baud ra te ge nerator. t he ba ud ra te i s c ontrolled by i ts own i nternal fre e runni ng 8-bi t t imer, t he period of which is determined by two factors. the frst of these is the value placed in the baud rate register brg and the second is the value of the brgh bit with the control register ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn dete rmines the formula that is used to calculate the baud rate. the value in the brg register, n, which is used in the following baud rate calculation formula determines the division factor. note that n is the decimal value placed in the brg register and has a range of between 0 and 255. baud rate (br) f sys [ ? 4(n+1)] f sys [1 ? (n+1)] by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register , the required baud rate can be setup. note that because the actual baud rate is determ ined using a discrete value, n, placed in the brg register , there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. na ? e d7 d ? d ? d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 d7~d0 : baud rate values by programming the brgh bit in ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup. for a clock frequency of 4mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br = [64(n+1)] re-arranging this equation gives n = (br64) - 1 giving a value for n = 4000000 (480064) -1 = 12.0208 to obtain the closest value, a decim al value of 12 should be placed into the brg register . this gives an actual or calculated baud rate value of br = 4000000 [64(12+1)] = 4808 therefore the error is equal to 4808-4800 4800 = 0.16%
rev. 1.30 134 de?e??e? 0?? ?01? rev. 1.30 13 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom uart t a ctl for data transfer , the uar t functio n utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uar t hardware, and can be setup to be even, odd or no parity . for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setti ng, which is the setting at power -on. the number of data bits and stop bits, along with t he pa rity, a re se tup by pr ogramming t he c orresponding b no, pr t, pr en, a nd st ops b its in the ucr1 register . the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received lsb frst. although the uar t transmitter and receiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. the basic on/of f function of the internal uar t function is controlled using the uar ten bit in the ucr1 register . if the uar ten, txen and rxen bits are set, then these two uar t pins will act as n ormal t x o utput p in a nd r x i nput p in r espectively. i f n o d ata i s b eing t ransmitted o n t he t x pin, then it will default to a logic high value. clearing t he uar ten b it wi ll d isable t he t x a nd r x p ins a nd a llow t hese t wo p ins t o b e i n fo ating state. when the uar t function is disabled the buf fer will be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uar t will also reset the error and status fa gs wi th bi ts t xen, rxe n, t xbrk, rxif , oe rr, fe rr, pe rr a nd nf be ing c leared while bi ts t idle, t xif a nd ri dle wi ll be se t. t he re maining c ontrol bi ts i n t he ucr 1, ucr2 and brg registers will remain unaf fected. if the uar ten bit in the ucr1 register is cleared while the uar t is active, then all pending transmissions and receptions will be immediately suspended and the uar t will be reset to a condition as defned above. if the uar t is then subsequently re- enabled, it will restart again in the same confguration. the f ormat o f t he d ata t o b e t ransferred i s c omposed o f v arious f actors su ch a s d ata b it l ength, parity on/of f, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register . the bno bit controls the number of data bits which can be set to either 8 or 9, the pr t bit controls the choice of odd or even parity , the pren bit controls the parity on/of f function and the st ops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address bit identifes the frame as an address character . the number of stop bits, which can be either one or two, is independent of the data length and are only to be used for t ransmitter. there is only one stop bit for receiver. 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 exa?ple of 9-?it data fo??ats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 t?ans?itte? re?eive? data fo??at the following diagram shows the trans mit and receive waveforms for both 8-bit and 9-bit data formats.
rev. 1.30 13 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 137 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom

uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register . at the transmitter core lies the transmitter shift register , more commonly known as the tsr, whos e data is obtained from the transmit d ata r egister, wh ich i s k nown a s t he t xr r egister. t he d ata t o b e t ransmitted i s l oaded into this txr register by the applic ation program. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr register , if it is available. it should be noted that the tsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator ha s de fned a shi ft c lock sourc e. however , t he t ransmission c an a lso be i nitiated by frst loading data into the txr register , after which the txen bit can be set. when a transmission of data begins, the tsr is normally empty , in which case a transfer to the txr register will result in an immed iate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will imm ediately cease and the transmitter will be reset. the tx output pin will be set in a foating state. when the uar t is transmitting data, the data is shifted on the tx pin from the shift register , with the leas t s ignificant bit firs t. in the trans mit mode, the tx r regis ter forms a buf fer betw een the internal bus and the transmitter shift register . it should be noted that if 9-bit data format has been selected, then the msb will be take n from the tx8 bit in the ucr1 register . the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, pr t, pren and st ops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txe n bit to ensure that the uar t transmi tter is enabled and the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr register . note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif is 0, data will be inhibited from being written to the txr register . clearing the txif fag is always achieved using the following software sequence: ? a usr register access ? a txr register write execution
rev. 1.30 13? de?e??e? 0?? ?01? rev. 1.30 137 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom the read-only txif fag is set by the uar t hardware and if set indic ates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set then the txif fag will generate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr register , which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register , resulting in the commencement of data transmission, and the txif bit being immediately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. t o clear the tidle bit the following software sequence is used: ? a usr register access ? a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be frst set by the application program and then cleared to generate the stop bits. t ransmitting a break character will not generate a transmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will fnish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. the uart is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr register . if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register . at the receive r core lies the receive serial shift register , commonly known as the rsr. the data which is received on the rx external input pin is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate , while the main receive serial shifter operates at the baud rate . after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register , if the register is empty. the data which is received on the external rx input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. when the uar t receiver is receiv ing data, the data is serially shifted in on the external rx input pin to the shift register , with the lea st signifcant bit lsb frst. the rxr register is a two byte deep fifo data buf fer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must ensure that the data is read from rxr before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows:
rev. 1.30 138 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 139 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ? make the correct selection of bno, pr t and pren bits to defne the word length and parity type. ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the uar t receiver is enabled and the rx pin is used as a uar t receiver pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received, the following sequence of events will occur: ? the rxif bit in the usr register will be set when rxr register has data available, at least one character can be read. ? when the content s of the shift register have been transferred to the rxr register and if the rie bit is set, then an interrupt will be generated. ? if during reception, a frame error , noise error , parity error , or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: ? a usr register access ? an rxr register read execution any break character received by the uar t will be managed as a framing error . the receiver will count and expect a certain number of bit times as specifed by the value s programmed into the bno and one st ops bit. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specifed by bno and one st op bit. the rxif bit is set, ferr is set, zeros are loaded into the receive data register , interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr fag, the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr fag set. the break character will be loaded into the buf fer and no further data will be received until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uar t registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. when the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status fag in the usr register , otherwise known as the ridle fag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. the read only receive interrupt fag rxif in the usr register is set by an edge generated by the receiver. an interrupt is generated if rie bit is 1, when a word is trans ferred from the receive shift re gister, rsr, t o t he re ceive da ta re gister, rxr. an ove rrun e rror c an a lso ge nerate a n interrupt if rie is 1.
rev. 1.30 138 de?e??e? 0?? ?01? rev. 1.30 139 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom maai ri es several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error C oerr fag the rxr register is composed of a two byte deep fifo data buf fer, where two bytes can be held in the fifo register , while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the rxr register . if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the o err flag can be cleared by an acces s to the u sr regis ter follow ed by a read to the rx r register. over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. i f n oise i s detected within a frame the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note t hat t he nf fa g i s r eset b y a usr r egister r ead o peration f ollowed b y a n r xr r egister r ead operation. the read only framing error fag, ferr, in the usr register , is set if a zero is detected instead of stop bits. if two stop bits are select ed, only the frst stop bit is detecte d, it must be high. if the frst stop bit is low , the ferr fag will be set. the ferr fag is buf fered along with the received data and is cleared on any reset. the read only parity error fag, perr, in the usr register , is set if the parity of the received word is incorrect. this error fag is only applicable if the parity is enabled, pren bit is 1, and if the parity type, odd or e ven i s se lected. t he re ad onl y pe rr fl ag i s buf fered a long wi th t he re ceived da ta bytes. it is cleared on any reset. it should be noted that the ferr and perr fags are buf fered along with the corresponding word and should be read before reading the data word.
rev. 1.30 140 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 141 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom uart ml tt tt several i ndividual uar t c onditions c an ge nerate a uar t i nterrupt. w hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. when any of these conditions are created, if its corresponding interrupt cont rol is enabled and the sta ck is not ful l, the progra m wil l jump to it s corresponding interrupt vector w here it can be s erviced before returning to the main program. four of thes e conditions h ave t he c orresponding usr r egister fa gs wh ich wi ll g enerate a uar t i nterrupt i f i ts associated interrupt enable control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address det ect condit ion, whic h is al so a uar t i nterrupt source, does not have an associa ted flag, but will generate a uar t interrupt when an address detect condition occurs if its function is e nabled by se tting t he adde n bi t i n t he ucr2 re gister. an rx pi n wa ke-up, whi ch i s a lso a uart interrupt source, does not have an associated fag, but will generate a uar t interrupt if the microcontroller i s woke n up from idl e0 or sl eep m ode by a fa lling e dge on t he rx pi n, i f t he wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a certain period of delay , commonly known as the system start-up t ime, for the oscillator to restart and stabilize before the system resumes normal operation. note t hat t he usr r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. the flags will be cleared automatically whe n c ertain a ctions a re t aken by t he uar t, t he de tails of whi ch a re gi ven i n t he uart regi ster se ction. the overal l uar t i nterrupt ca n be di sabled or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed. usr registe? t?ans?itte? e?pty flag txif 0 1 wake inte??upt signal to mcu t?ans?itte? idle flag tidle re?eive? ove??un flag oerr re?eive? data availa?le rxif rx pin wake-up ucr? registe? or 0 1 adden 0 1 rie 0 1 tiie 0 1 teie 0 1 rx7 if bno=0 rx8 if bno=1 ucr? registe? uart inte??upt request flag urf 0 1 ure 0 1 emi uart inte??upt st?u?tu?e
rev. 1.30 140 de?e??e? 0?? ?01? rev. 1.30 141 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ass dtt m setting t he ad dress de tect mo de b it, adde n, i n t he uc r2 r egister, e nables t his sp ecial m ode. if this bit is enabled then an additional qualifier will be placed on the generation of a receiver data a vailable interrupt, which is requested by the rxif fag. if the adden bit is 1, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the related interrupt enable control bit and the emi bit must also be enabled for correct interrupt generatio n. this highest address bit is the 9 th bit if bno bit is 1 or the 8 th bit if bno bit is 0. if this bit is high, then the received word will be defned as an address rather than data. a data a vailable interrupt will be generated every time the last bit of the received word is set. if the adden bit is 0, then a receiver data a vailable interrupt will be generated each time the rxif flag i s se t, i rrespective o f t he d ata l ast b it st atus. t he a ddress d etect m ode a nd p arity e nable a re mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit pren to zero. 0 0 1 1 0 1 when the the device system clock is switched of f, the uar t will cease to function. if the device executes the hal t instruction and switches of f the system clock while a transmission is still in progres s, then the trans mission w ill be paus ed until the u art clock source derived from the microcontroller is activated. in a similar way , if the device executes the hal t instruction and switches of f the system clock while receiving data, then the reception of data will likewise be paused. when the device enters the idle or sleep mode, note that the usr, ucr1, ucr2, transmit and recei ve registers, as well as the brg register will not be af fected. it is recommended to make sure first that the ua rt data transmis sion or reception has been finished before the microcontroller enters the idle or sleep mode. the ua rt function contains a receiver rx pin wake-up function, which is enabled or disabled by the w ake bit in the ucr2 register . if this bit, along with the uar t enable bit, uar ten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the device enters the idle0 or sleep mode, then a falling edge on the rx pin will wake up the device from the idle0 or sl eep mo de. no te t hat a s i t t akes c ertain sy stem c lock c ycles a fter a wa ke-up, b efore n ormal microcontroller operation resumes, any data received during this time on the rx pin will be ignored. for a uar t wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uar t interrupt enable bit, ure, must also be set. if these two bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed.
rev. 1.30 14 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 143 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom cd com ti the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with certain pin on the i/o ports. the lcd signals are generated using the application program. an external lcd panel can be driven using this device by confguring the i/o pins as common pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/of f function also controls the bias voltage setup function . this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation. the s comen bit in the s comc register is the overall mas ter control for the lcd driver . the lcd scomn pin is selected to be used for lcd driving by the corresponding pin-shared function selection bits. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation.
lcd bias current control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd p anel whi ch a re b eing u sed. t he b ias re sistor c hoice i s i mplemented u sing t he ise l1 a nd isel0 bits in the scomc register. na ? e isel1 isel0 scomen r/w r/w r/w r/w por 0 0 0 bit 7 unimplemented, read as 0 bit 6~5 : select resistor for r type lcd bias current (v dd =5v) 00: 2100k (1/2 bias), i bias = 25a 01: 250k (1/2 bias), i bias = 50a 10: 225k (1/2 bias), i bias = 100a 11: 212.5k (1/2 bias), i bias = 200a bit 4 : lcd control bit 0: disable 1: enable when scomen is set, it will turn on the dc path of resistor to generate 1/2 v dd bias voltage. bit 3~0 unimplemented, read as 0
rev. 1.30 14? de?e??e? 0?? ?01? rev. 1.30 143 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the devices contain several external interrupts and internal interrupts functions. the external interrupt is generated by the action of the external int0~int1 pins, while the internal interrupts are generated by various internal functions such as the tms, t ime base, eeprom, sim, uart and the a/d converter. overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. t he frst i s t he int c0~intc2 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. glo ? al emi intn pin intne intnf n=0 o ? 1 a/d conve ? te ? ade adf multi-fun ? tion mfne mfnf n=0~ ? ti ? e base tbne tbnf n=0 o ? 1 eeprom dee def ctm ctmane ctmanf n=0 o ? 1 ctmpne ctmpnf ptm ptmane ptmanf n=0~3 ptmpne ptmpnf sim sime simf uart ure urf inte??upt registe? bit na?ing conventions registe? na?e bit 7 ? ? 4 3 ? 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 tb1f tb0f int0f tb1e tb0e int0e emi intc1 int1f adf def mf0f int1e ade dee mf0e intc ? (ht ?? f004 ? ) simf mf ? f mf1f sime mf ? e mf1e intc ? (ht ?? f008 ? ) urf simf mf ? f mf1f ure sime mf ? e mf1e mfi0 ptma1f ptmp1f ptma0f ptmp0f ptma1e ptmp1e ptma0e ptmp0e mfi1 ptma3f ptmp3f ptma ? f ptmp ? f ptma3e ptmp3e ptma ? e ptmp ? e mfi ? ctma1f ctmp1f ctma0f ctmp0f ctma1e ctmp1e ctma0e ctmp0e inte??upt registe? contents
rev. 1.30 144 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 14? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom te rist it 6 4 2 0 na ? e int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as 0 bit 3 ~ 2 int1s1, int1s0 : int1 interrupt active edge selection 00: disable 01: rising edge 10: falling edge 11: dual edges bit 1 ~ 0 int0s1, int0s0 : int0 interrupt active edge selection 00: disable 01: rising edge 10: falling edge 11: dual edges na ? e tb1f tb0f int0f tb1e tb0e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 tb1f : t ime base 1 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f : t ime base 0 interrupt request flag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request flag 0: no request 1: interrupt request bit 3 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 2 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.30 144 de?e??e? 0?? ?01? rev. 1.30 14 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tc rist it 6 4 2 0 na ? e int1f adf def mf0f int1e ade dee mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 int1f : int1 interrupt request flag 0: no request 1: interrupt request bit 6 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 4 mf0f : multi-function 0 interrupt request flag 0: no request 1: interrupt request bit 3 int1e : int1 interrupt control 0: disable 1: enable bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 mf0e : multi-function 0 interrupt control 0: disable 1: enable
rev. 1.30 14 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 147 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tc2 rist HT66F0042 it 6 4 2 0 na ? e simf mf ? f mf1f sime mf ? e mf1e r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 simf : sim interrupt request flag 0: no request 1: interrupt request bit 5 mf2f : multi-function 2 interrupt request flag 0: no request 1: interrupt request bit 4 mf1f : multi-function 1 interrupt request flag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 sime : sim interrupt control 0: disable 1: enable bit 1 mf2e : multi-function 2 interrupt control 0: disable 1: enable bit 0 mf1e : multi-function 1 interrupt control 0: disable 1: enable
rev. 1.30 14? de?e??e? 0?? ?01? rev. 1.30 147 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tc2 rist ht66f0082 it 6 4 2 0 na ? e urf simf mf ? f mf1f ure sime mf ? e mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 urf : uart interrupt request flag 0: no request 1: interrupt request bit 6 simf : sim interrupt request flag 0: no request 1: interrupt request bit 5 mf2f : multi-function 2 interrupt request flag 0: no request 1: interrupt request bit 4 mf1f : multi-function 1 interrupt request flag 0: no request 1: interrupt request bit 3 ure : uart interrupt control 0: disable 1: enable bit 2 sime : sim interrupt control 0: disable 1: enable bit 1 mf2e : multi-function 2 interrupt control 0: disable 1: enable bit 0 mf1e : multi-function 1 interrupt control 0: disable 1: enable
rev. 1.30 148 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 149 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom mf0 rist it 6 4 2 0 na ? e ptma1f ptmp1f ptma0f ptmp0f ptma1e ptmp1e ptma0e ptmp0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ptma1f : ptm1 comparator a match interrupt request flag 0: no request 1: interrupt request bit 6 ptmp1f : ptm1 comparator p match interrupt request flag 0: no request 1: interrupt request bit 5 ptma0f : ptm0 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 ptmp0f : ptm0 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3 ptma1e : ptm1 comparator a match interrupt control 0: disable 1: enable bit 2 ptmp1e : ptm1 comparator p match interrupt control 0: disable 1: enable bit 1 ptma0e : ptm0 comparator a match interrupt control 0: disable 1: enable bit 0 ptmp0e : ptm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.30 148 de?e??e? 0?? ?01? rev. 1.30 149 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom mf rist it 6 4 2 0 na ? e ptma3f ptmp3f ptma ? f ptmp ? f ptma3e ptmp3e ptma ? e ptmp ? e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ptma3f : ptm3 comparator a match interrupt request flag 0: no request 1: interrupt request bit 6 ptmp3f : ptm3 comparator p match interrupt request flag 0: no request 1: interrupt request bit 5 ptma2f : ptm2 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 ptmp2f : ptm2 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3 ptma3e : ptm3 comparator a match interrupt control 0: disable 1: enable bit 2 ptmp3e : ptm3 comparator p match interrupt control 0: disable 1: enable bit 1 ptma2e : ptm2 comparator a match interrupt control 0: disable 1: enable bit 0 ptmp2e : ptm2 comparator p match interrupt control 0: disable 1: enable
rev. 1.30 1 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?1 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom mf2 rist it 6 4 2 0 na ? e ctma1f ctmp1f ctma0f ctmp0f ctma1e ctmp1e ctma0e ctmp0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ctma1f : ctm1 comparator a match interrupt request flag 0: no request 1: interrupt request bit 6 ctmp1f : ctm1 comparator p match interrupt request flag 0: no request 1: interrupt request bit 5 ctma0f : ctm0 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 ctmp0f : ctm0 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3 ctma1e : ctm1 comparator a match interrupt control 0: disable 1: enable bit 2 ctmp1e : ctm1 comparator p match interrupt control 0: disable 1: enable bit 1 ctma0e : ctm0 comparator a match interrupt control 0: disable 1: enable bit 0 ctmp0e : ctm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.30 1?0 de?e??e? 0?? ?01? rev. 1.30 1 ? 1 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tt oati when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/ d conversion completion etc, the relevant interrupt request fag wi ll be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.30 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?3 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom int0 pin int0f int0e emi 04h emi 08h emi 10h emi ?0h ptm3 p ptmp3f ptmp3e inte??upt na?e request flags ena?le bits maste? ena?le ve?to? emi auto disa?led in isr p?io?ity high low ptm1 p ptmp1f ptmp1e ptm1 a ptma1f ptma1e m. fun?t. 0 mf0f mf0e inte??upts ?ontained within multi- fun?tion inte??upts xxe ena?le bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr m. fun?t. 1 mf1f mf1e ptm3 a ptma3f ptma3e emi ?4h m. fun?t. ? mf?f mf?e ptm? p ptmp?f ptmp?e ptm? a ptma?f ptma?e uart uartf uarte emi ?8h emi ?ch sim simf sime ti?e base 0 tb0f tb0e emi 0ch ti?e base 1 tb1f tb1e ptm0 p ptmp0f ptmp0e ptm0 a ptma0f ptma0e a/d adf ade emi 18h emi 14h eeprom def dee int1 pin int1f int1e emi 1ch ctm1 p ctmp1f ctmp1e ctm1 a ctma1f ctma1e ctm0 p ctmp0f ctmp0e ctm0 a ctma0f ctma0e uart inte??upt is only ex ists in the fo? ht??f008? inte??upt st?u?tu?e exte?nal inte??upt the e xternal i nterrupt i s c ontrolled b y si gnal t ransitions o n t he p ins i nt0~int1. an e xternal interrupt re quest wi ll t ake pl ace whe n t he e xternal i nterrupt re quest fl ag, int nf, i s se t, whi ch will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. t o allow the program to branch to the interrupt vector address, the global interrupt enable bit, emi, and the external interrupt enable bit, intne, must fi rst be set. additi onally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be confgured as external interrupt pins by setting the pin-shared registers. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interr upt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the exter nal interrupt request fag, intnf , will be automatica lly reset and the emi bit will be automatically cleared to disable other interrupts. note that the pull-high resistor selection on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function.
rev. 1.30 1?? de?e??e? 0?? ?01? rev. 1.30 1 ? 3 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom mltiti tt within these devices there are up to three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf2f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupt s, will not be automatically reset and must be manually reset by the application program. the devices conta in an a/d converter which has its own independent interrupt. the a/d converter interrupt is controlled by the termin ation of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the inte rrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converte r interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt flag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of t he t ime base inte rrupt i s t o provi de an i nterrupt si gnal at fixe d t ime peri ods. their clock sources originate from the internal clock source f tb , the clock of which can be selected between the f sys /4 and f tbc . this f tb input clock passes through a divide r, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose v alue r anges. t he c lock so urce t hat g enerates f tb , wh ich i n t urn c ontrols t he t ime b ase interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.
rev. 1.30 1 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tc rist it 6 4 2 0 na ? e tbon tbck tb11 tb10 lxtlp tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon : tb0 and tb1 control bit 0: disable 1: enable bit 6 tbck : select f clock 0: f tbc 1: f /4 bit 5 ~ 4 tb1 1 ~ tb10 : select t ime base 1 t ime-out period 00: 4096/f 01: 8192/f 10: 16384/f 11: 32768/f bit 3 lxtlp : lxt low power control 0: disable 1: enable bit 2 ~ 0 tb02 ~ tb00 : select t ime base 0 t ime-out period 000: 256/f 001: 512/f 010: 1024/f 011: 2048/f 100: 4096/f 101: 8192/f 110: 16384/f 111: 32768/f

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time base interrupt eeprom interrupt an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the eeprom interrupt request fag, def, will also be automatically cleared.
rev. 1.30 1?4 de?e??e? 0?? ?01? rev. 1.30 1 ?? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tm tts each of the compact and periodic tms has two interrupts, one comes from the comparator a match situation a nd t he ot her c omes from t he c omparator p m atch si tuation. al l of t he t m i nterrupts a re contained within the multi-function interrupts. for each of the tms there are two interrupt request fags x tmpnf a nd x tmanf a nd t wo e nable b its x tmpne a nd x tmane. a t m i nterrupt r equest will take place when any of the tm request flags are set, a situation which occurs when a tm comparator p or comparator a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the respective tm interrupt enable bit, and associated multi-function interrupt enable bit, mfnf , must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant tm interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. the serial interface module interrupt, also known as the sim interrupt, is controlled by the spi or i 2 c data transfer . a sim interrupt request will take place when the sim interrupt request fag, simf , is set, which occurs when a byte of data has been received or transmitted by the sim interface, an i 2 c slave address match or i 2 c bus time-out occurrence. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi and the serial interface interrupt enable bit, sime, must frst be set. when the interrupt is enabled, the stack is not full and any of the above described situations occurs, a subroutine call to the respective sim interrupt vector, will t ake p lace. w hen t he se rial i nterface i nterrupt i s se rviced, t he e mi b it wi ll b e a utomatically cleared to disable other interrupts. the simf fag will also be automatically cleared. the uar t t ransfer interrupt is controlled by several uar t transfer conditions. when one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and uar t interrupt enable bit, ure, must frst be set. when the interrupt is enabled, the stack is not full and any of the conditions described above occurs, a subroutine call to the uar t interrupt vector , will take place. when the interrupt is serviced, the uar t interrupt fag, urf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function.
rev. 1.30 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?7 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom pai csiatis by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the m ulti-function interrupt reques t f ags, m f0f~mf2f, w ill be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programmi ng tools, onc e they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. 1 low speed syste ? os ? illato ? sele ? tion: lxt lirc ? hirc f ? equen ? y sele ? tion: 8mhz 1 ? mhz 1 ? mhz 3 lxt option: integ ? ated resisto ? and capa ? ito ? exte ? nal resisto ? and capa ? ito ?
rev. 1.30 1?? de?e??e? 0?? ?01? rev. 1.30 1 ? 7 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom aliati ciits
HT66F0042
ht66f0082
rev. 1.30 1 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?9 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom stti t tti central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of several kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator . one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions such as inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.30 1?8 de?e??e? 0?? ?01? rev. 1.30 1 ? 9 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ial a rtat oati the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been c arried out. t his i s done by pl acing a re turn i nstruction ret i n t he subrout ine whi ch wi ll cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.30 1 ? 0 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?1 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom stti t a the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address add a ? [ ? ] add data me ? o ? y to acc 1 z ? c ? ac ? ov addm a ? [ ? ] add acc to data me ? o ? y 1 note z ? c ? ac ? ov add a ? x add i ?? ediate data to acc 1 z ? c ? ac ? ov adc a ? [ ? ] add data me ? o ? y to acc with ca ?? y 1 z ? c ? ac ? ov adcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y 1 note z ? c ? ac ? ov sub a ? x su ? t ? a ? t i ?? ediate data f ? o ? the acc 1 z ? c ? ac ? ov sub a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc 1 z ? c ? ac ? ov subm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y 1 note z ? c ? ac ? ov sbc a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov sbcm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y 1 note z ? c ? ac ? ov daa [ ? ] de ? i ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 note c logi? ope?ation and a ? [ ? ] logi ? al and data me ? o ? y to acc 1 z or a ? [ ? ] logi ? al or data me ? o ? y to acc 1 z xor a ? [ ? ] logi ? al xor data me ? o ? y to acc 1 z andm a ? [ ? ] logi ? al and acc to data me ? o ? y 1 note z orm a ? [ ? ] logi ? al or acc to data me ? o ? y 1 note z xorm a ? [ ? ] logi ? al xor acc to data me ? o ? y 1 note z and a ? x logi ? al and i ?? ediate data to acc 1 z or a ? x logi ? al or i ?? ediate data to acc 1 z xor a ? x logi ? al xor i ?? ediate data to acc 1 z cpl [ ? ] co ? ple ? ent data me ? o ? y 1 note z cpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc 1 z in??e?ent & de??e?ent inca [ ? ] in ?? e ? ent data me ? o ? y with ? esult in acc 1 z inc [ ? ] in ?? e ? ent data me ? o ? y 1 note z deca [ ? ] de ?? e ? ent data me ? o ? y with ? esult in acc 1 z dec [ ? ] de ?? e ? ent data me ? o ? y 1 note z rotate rra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc 1 none rr [ ? ] rotate data me ? o ? y ? ight 1 note none rrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y 1 note c rla [ ? ] rotate data me ? o ? y left with ? esult in acc 1 none rl [ ? ] rotate data me ? o ? y left 1 note none rlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y 1 note c
rev. 1.30 1?0 de?e??e? 0?? ?01? rev. 1.30 1 ? 1 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom mi dsiti cls fla at data m mov a ? [ ? ] move data me ? o ? y to acc 1 none mov [ ? ] ? a move acc to data me ? o ? y 1 note none mov a ? x move i ?? ediate data to acc 1 none bit ope?ation clr [ ? ].i clea ? ? it of data me ? o ? y 1 note none set [ ? ].i set ? it of data me ? o ? y 1 note none b?an?h ope?ation jmp add ? ju ? p un ? onditionally ? none sz [ ? ] skip if data me ? o ? y is ze ? o 1 note none sza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc 1 note none sz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o 1 note none snz [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o 1 note none siz [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o 1 note none sdz [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o 1 note none siza [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none sdza [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none call add ? su ?? outine ? all ? none ret retu ? n f ? o ? su ?? outine ? none ret a ? x retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc ? none reti retu ? n f ? o ? inte ?? upt ? none ta?le read ope?ation tabrd [ ? ] read table (specifc page) to tblh and data memory ? note none tabrdc [ ? ] read ta ? le ( ? u ?? ent page) to tblh and data me ? o ? y ? note none tabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y ? note none mis?ellaneous nop no ope ? ation 1 none clr [ ? ] clea ? data me ? o ? y 1 note none set [ ? ] set data me ? o ? y 1 note none clr wdt clea ? wat ? hdog ti ? e ? 1 to ? pdf clr wdt1 p ? e- ? lea ? wat ? hdog ti ? e ? 1 to ? pdf clr wdt ? p ? e- ? lea ? wat ? hdog ti ? e ? 1 to ? pdf swap [ ? ] swap ni ?? les of data me ? o ? y 1 note none swapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc 1 none halt ente ? powe ? down ? ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the t o and pdf flags may be af fected by the execution sta tus. t he t o a nd pdf fl ags a re c leared a fter bot h clr w dt1 a nd clr w dt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.30 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?3 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom instruction defnition add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.30 1?? de?e??e? 0?? ?01? rev. 1.30 1 ? 3 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ca a subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.30 1 ? 4 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom cpa complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.30 1?4 de?e??e? 0?? ?01? rev. 1.30 1 ?? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom mp a jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.30 1 ?? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?7 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom ret a return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.30 1?? de?e??e? 0?? ?01? rev. 1.30 1 ? 7 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom rra rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.30 1 ? 8 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 1?9 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom da skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.30 1?8 de?e??e? 0?? ?01? rev. 1.30 1 ? 9 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom um a subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.30 170 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 171 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom tard read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.30 170 de?e??e? 0?? ?01? rev. 1.30 171 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom paa ati note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product t ape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.30 17 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 173 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 20i op 00il otli disis symbol dimensions in inch min. nom. max. a 0.40 ? bsc b 0. ? 9 ? bsc c 0.01 ? 0.0 ? 0 c 0. ? 04 bsc d 0.104 e 0.0 ? 0 bsc f 0.004 0.01 ? g 0.01 ? 0.0 ? 0 h 0.008 0.013 0 8 sy??ol di?ensions in ?? min. no?. max. a 10.30 bsc b 7. ? bsc c 0.31 0. ? 1 c 1 ? .8 bsc d ? . ?? e 1. ? 7 bsc f 0.10 0.30 g 0.40 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.30 17? de?e??e? 0?? ?01? rev. 1.30 173 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 24i op 00il otli disis symbol dimensions in inch min. nom. max. a 0.40 ? bsc b 0. ? 9 ? bsc c 0.01 ? 0.0 ? 0 c 0. ? 0 ? bsc d 0.104 e 0.0 ? 0 bsc f 0.004 0.01 ? g 0.01 ? 0.0 ? 0 h 0.008 0.013 0 8 sy??ol di?ensions in ?? min. no?. max. a 10.30 bsc b 7. ? 0 bsc c 0.31 0. ? 1 c 1 ? .4 bsc d ? . ?? e 1. ? 7 bsc f 0.10 0.30 g 0.40 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.30 174 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 17? de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 28i op 00il otli disis symbol dimensions in inch min. nom. max. a 0.40 ? bsc b 0. ? 9 ? bsc c 0.01 ? 0.0 ? 0 c 0.70 ? bsc d 0.104 e 0.0 ? 0 bsc f 0.004 0.01 ? g 0.01 ? 0.0 ? 0 h 0.008 0.013 0 8 sy??ol di?ensions in ?? min. no?. max. a 10.30 bsc b 7. ? 0 bsc c 0.31 0. ? 1 c 17.90 bsc d ? . ?? e 1. ? 7 bsc f 0.10 0.30 g 0.40 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.30 174 de?e??e? 0?? ?01? rev. 1.30 17 ? de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 20i op 0il otli disis symbol dimensions in inch min. nom. max. a 0. ? 3 ? bsc b 0.1 ? 4 bsc c 0.008 0.01 ? c 0.341 bsc d 0.0 ? 9 e 0.0 ?? bsc f 0.004 0.010 g 0.01 ? 0.0 ? 0 h 0.004 0.010 0 8 sy??ol di?ensions in ?? min. no?. max. a ? .0 bsc b 3.9 bsc c 0. ? 0 0.30 c 8. ?? bsc d 1.7 ? e 0. ? 3 ? bsc f 0.10 0. ?? g 0.41 1. ? 7 h 0.10 0. ?? 0 8
rev. 1.30 17 ? de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 177 de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 24i op 0il otli disis symbol dimensions in inch min. nom. max. a 0. ? 3 ? bsc b 0.1 ? 4 bsc c 0.008 0.01 ? c 0.341 bsc d 0.0 ? 9 e 0.0 ?? bsc f 0.004 0.010 g 0.01 ? 0.0 ? 0 h 0.004 0.010 0 8 sy??ol di?ensions in ?? min. no?. max. a ? .0 bsc b 3.9 bsc c 0. ? 0 0.30 c 8. ?? bsc d 1.7 ? e 0. ? 3 ? bsc f 0.10 0. ?? g 0.41 1. ? 7 h 0.10 0. ?? 0 8
rev. 1.30 17? de?e??e? 0?? ?01? rev. 1.30 177 de ? e ?? e ? 0 ?? ? 01 ? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom 28i op 0il otli disis symbol dimensions in inch min. nom. max. a 0. ? 3 ? bsc b 0.1 ? 4 bsc c 0.008 0.01 ? c 0.390 bsc d 0.0 ? 9 e 0.0 ?? bsc f 0.004 0.010 g 0.01 ? 0.0 ? 0 h 0.004 0.010 0 8 sy??ol di?ensions in ?? min. no?. max. a ? .0 bsc b 3.9 bsc c 0. ? 0 0.30 c 9.9 bsc d 1.7 ? e 0. ? 3 ? bsc f 0.10 0. ?? g 0.41 1. ? 7 h 0.10 0. ?? 0 8
rev. 1.30 178 de ? e ?? e ? 0 ?? ? 01 ? rev. 1.30 pb de?e??e? 0?? ?01? HT66F0042/ht66f0082 a/d flash mcu with eeprom HT66F0042/ht66f0082 a/d flash mcu with eeprom copy ? ight ? ? 01 ? ? y holtek semiconductor inc. the info ?? ation appea ? ing in this data sheet is ? elieved to ? e a ?? u ? ate at the ti ? e of pu ? li ? ation. howeve ?? holtek assu ? es no ? esponsi ? ility a ? ising f ? o ? the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek ? akes no wa ?? anty o ? ? ep ? esentation that su ? h appli ? ations will ? e suita ? le without fu ? the ? ? odifi ? ation ? no ? ? e ? o ?? ends the use of its p ? odu ? ts fo ? appli ? ation that ? ay p ? esent a ? isk to hu ? an life due to ? alfun ? tion o ? othe ? wise. holtek's p ? odu ? ts a ? e not autho ? ized fo ? use as ?? iti ? al ? o ? ponents in life suppo ? t devi ? es o ? syste ? s. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek. ? o ? .tw.

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